SLVSGE8B November   2022  – August 2024 TPS35-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Supervisor
      2. 7.3.2 Timeout Watchdog Timer
        1. 7.3.2.1 tWD Timer
        2. 7.3.2.2 Watchdog Enable Disable Operation
        3. 7.3.2.3 tSD Watchdog Start Up Delay
        4. 7.3.2.4 SET Pin Behavior
      3. 7.3.3 Manual RESET
      4. 7.3.4 RESET and WDO Output
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed watchdog Timing
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Watchdog Timer Functionality
        1. 8.1.2.1 Factory-Programmed watchdog Timing
        2. 8.1.2.2 Adjustable Capacitor Timings
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting the Voltage Threshold
          2. 8.2.1.2.2 Meeting the Watchdog Timeout Period
          3. 8.2.1.2.3 Setting the Reset Delay
          4. 8.2.1.2.4 Setting the Startup Delay and Output Topology
          5. 8.2.1.2.5 Calculating the RESET Pullup Resistor
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2.3 tSD Watchdog Start Up Delay

The TPS35-Q1 supports watchdog startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted. This feature allows time for the host complete boot process before watchdog monitoring can take over. The start up delay helps avoid unexpected WDO or RESET assert events during boot. The tSD time is predetermined based on the device part number selected. Refer Section 4 section for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec start up delay options.

To exit tSD frame, one of the following event must occur:

  • The host provides a valid pulse transition on the WDI pin.
  • Change in logic state of SET[1:0].
  • Toggling of the WD_EN pin.
The device enters watchdog monitoring phase after the device exits the tSD frame.

Failure to provide one of the exit condition within tSD triggers the watchdog error by asserting the WDO output pin for tD, this is observed in Figure 7-8. For devices with only RESET output, the RESET pin is asserted.

The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in Section 7.3.2.2 section.

Figure 7-8 shows the operation for tSD time frame.

TPS35-Q1 tSD Frame Behavior Figure 7-8 tSD Frame Behavior