TPS3820/3/4/8-xx-Q1 devices have a watchdog timer that must be periodically triggered by either a positive or negative transition at WDI to avoid a reset signal being issued. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, ttout, RESET becomes active for the time period td. This event also reinitializes the watchdog timer.
The watchdog timer can be disabled by disconnecting the WDI pin from the system. If the WDI pin detects that it is in a high-impedance state the TPS3820/3/4/8-xx-Q1 will generate its own WDI pulse to ensure that RESET does not assert. If this behavior is not desired place a 1-kΩ resistor from WDI to ground. This resistor will help ensure that the TPS3820/3/4/8-xx-Q1 detects that WDI is not in a high-impedance state.
In applications where the input to the WDI pin is active (transitioning high and low) when the TPS3820/3/4/8-xx-Q1 is asserting RESET, RESET will be stuck at a logic low after the input voltage returns above VIT–. If the application requires that input to WDI be active when the reset signal is asserted, then use a FET to decouple the WDI signal. An external FET decouples the WDI signal by disconnecting the WDI input when RESET is asserted. For more details on this, see Decoupling WDI During Reset Event for more details.