7.3.6.1 Soft Start and Foldback Functions

A capacitor on the SS3 terminal sets the converter soft start. Pulling the enable pin on EN3 high activates soft start. During soft start or whenever the voltage on VSENSE3 falls below limits given by ƒ_SW-f-back, the converter switches to a frequency foldback of ƒ_sw / 2 to help control the coil current. In addition to the frequency foldback, implementation of current foldback reduces power dissipation to protect the converter against an output short to ground. Like in the buck controllers, the current foldback reduces the maximum peak current limit depending on the voltage on the VSENSE3 pin. Figure 9 shows the characteristic of current foldback.

7.3.6.2 Current-Mode Control and Current-Limit Protection

Measurement of the coil peak current is by use of the high-side integrated FET; peak-current regulation occurs in each switching cycle in accordance with the voltage on the COMP3 pin. COMP3 is the output of a transconductance error amplifier of the voltage feedback loop for Buck3, as COMP1 and COMP2 are for controllers Buck1 and Buck2. COMP3 sets the target for the peak current comparator (inner current loop) and serves as frequency compensation of the voltage loop using a type II compensation network.

Clamping the voltage on the COMP3 node realizes the positive current limit. The positive clamping level depends on the voltage on the VSENSE3 pin, as described previously. The device also implements clamping for low voltage on the COMP3 pin, thereby speeding up the transient response after output overshoot. For stability of the current loop, during the switching cycle the internal slope compensation adjusts the current limit set by COMP3.

For correct operation of the slope compensation, the coil used for Buck3 must satisfy the following:

Reaching the positive current limit during the high PWM phase resets the PWM. The high-side FET turns off and the low part of the cycle is initiated. On detecting an overcurrent condition such as an output short to a supply during the PWM low phase, the low-side FET turns off until the end of the given cycle, to allow the coil current to flow through the body diode of the high-side FET.

7.3.6.3 Operation in Dropout and Undervoltage Protection

This converter is capable of operating with a low input-to-output voltage difference. In dropout operation, the integrated high-side MOSFET stays on continuously. In every fourth clock cycle, the device limits the duty cycle to 95% in order to charge the bootstrap capacitor at BOOT3. This allows a maximum duty cycle of 98.75% for the buck converter. In this mode, the output tracks the input until initiation of the internal undervoltage lockout due to low supply voltage on the VSUP pin.

Thermal shutdown monitors the virtual junction temperature of the integrated FETs. When T_J exceeds 170°C, both the high- and low-side switches turn off. The converter returns to normal operation when the temperature decreases to the acceptable level (typically T_J = 150°C)

7.3.6.4 Slew Rate Control (SLEW)

The setting on the SLEW terminal controlss the slew for Buck3. Setting the slew rate to logic high (slowest slew rate) extends the minimum on-time of the buck converter by 5% of the clock period.

7.4.1.1 Setting the Operating Frequency

The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending on the resistor value at the RT pin. Tying this pin to ground sets the default switching frequency to 400 kHz. A resistor connected to RT can also set the frequency according to the formula:

It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz. The device detects clock pulses at this pin, and an internal PLL locks onto the external clock within the specified range. The device can also detect a loss of clock at this pin, and detection of clock loss for t_{SW-Trans-delay}sets the switching frequency to the internal oscillator. The two buck controllers operate at the same switching frequency, 180 degrees out of phase.

7.4.1.2 Feedback Inputs

Choose the resistor feedback divider networks connected to the VSENSEx (feedback) pins to set the output voltages. Make the choice such that the regulated voltages at the VSENSEx pins equal 0.8 V. The VSENSEx pins have 100-nA pullup current sources as a protection feature in case the pins open up as a result of physical damage.

Equation 3.

where

• R_TOP is the resistor from V_OUTx to VSENSEx
• R_BOTTOM is the resistor from VSENSEx to ground.

7.4.1.3 Soft-Start Inputs

In order to avoid large inrush currents, both buck controllers have independent programmable soft-start timing. The voltage at the SSx pins acts as the soft-start reference voltage. A 1-µA pullup current is available at the SSx pins, and by choosing a suitable capacitor one can obtain a desired soft-start ramp speed. After start-up, the pullup current ensures that pins SSx are higher than the internal reference of 0.8 V, which then becomes the reference for the buck controllers. The required capacitor for ∆t, the desired soft-start time, is given by:

Equation 4.

where

• I_SS = 1 µA (typical)
• ∆V = 0.8 V

Alternatively, one can use the soft-start pins as tracking inputs. In this case, connect the pins to the supply to be tracked via a suitable divider network.

7.4.1.4 Current-Mode Operation

Peak current-mode control regulates the peak current through the inductor such that the output voltage maintains its set value. The error between the feedback voltage at VSENSEx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as the target for the peak inductor current. This target provides a comparison for the current through the inductor, sensed as a differential voltage at S1-S2 for Buck1 and S3-S4 for Buck2, and compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at VSENSEx, causing COMPx to fall or rise, respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. In this way, the device maintains the output voltage in regulation.

The high-side N-channel MOSFET turns on at the beginning of each clock cycle and remains on until the inductor current reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay), the lower N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET stays on continuously. In every fourth clock cycle, the duty cycle is limited to 95% in order to charge the bootstrap capacitor at BOOTx. This allows a maximum duty cycle of 98.75% for the buck regulators. Thus, during dropout the buck regulators switch at one-fourth of the normal frequency.

7.4.1.5 Current Sensing and Current Limit With Foldback

Clamping the maximum value of COMPx is such as to limit the maximum current through the inductor to a specified value. When the output of the buck regulator (and hence the feedback value at VSENSEx) falls to a low value due to a short circuit or overcurrent condition, the clamping voltage at the COMPx successively decreases, thus providing current foldback protection. This protects the high-side external MOSFET from excess current (forward-direction current limit).

Similarly, if due to a fault condition the output shorts to a high voltage and turns the low-side MOSFET fully on, the COMPx node drops low. The device holds COMPx at a low level as well in order to limit the maximum current in the low-side MOSFET (reverse direction current limit).

An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This value specification is at low duty cycles only. At typical duty cycle conditions around 40% (assuming 5-V output and 12-V input), 50 mV is a more reasonable value, considering the slope compensation and tolerances. The typical characteristics in Figure 18 and Figure 12 provide a guide for using the correct current-limit sense voltage.

The current-sense pins Sx are high-impedance pins with low leakage across the entire output range. These pin characteristics allow DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 17 shows DCR sensing. Here the series resistance (DCR) of the inductor serves as the sense element. Place the filter components close to the device for noise immunity. Remember that while DCR sensing gives high efficiency, it is less accurate due to the temperature sensitivity and a wide variation of the parasitic series resistance of the inductor. Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing.

Figure 17. Overcurrent Sensing and Control

7.4.1.6 Slope Compensation

Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable current-mode operation in all conditions. For optimal performance of this circuit, satisfy the following condition in the choice of inductor and sense resistor:

Equation 5.

where

• L is the buck regulator inductor in henries
• R_S is the sense resistor in ohms
• f_sw is the buck regulator switching frequency in Hz

Figure 18. Peak Current-Sense Voltage versus Duty Cycle

7.4.1.7 Reset Outputs and Filter Delays

Each buck controller has an independent reset comparator monitoring the feedback voltage at the VSENSEx pins and indicating whether the output voltage has fallen below the specified reset threshold. The reset indicator is available as an open-drain output at the RSTx pins. An internal 50-kΩ pullup resistor to S2 or S4 is available, or one can use an external resistor. When a buck controller shuts down, the device pulls down the power-good outputs internally. Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow through the resistor when the buck controller powers down.

In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the device implements an internal delay of t_deglitch for de-glitching. The output voltage reaching its set value after a start-up ramp or negative transient asserts the power-good indicator high (releases the open-drain pin) after a delay of t_delay, at least t_{delay_fix}. A use of this is to delay the reset to the circuits being powered from the buck regulator rail. Program the delay of this circuit by using a suitable capacitor at the Rdelay pin according to Equation 6:

Power-Good Output Delay

Equation 6.

where

• C_Rdelay is the capacitor value in farads on the Rdelay pin.

An open on the Rdelay pin sets the delay to a default value of 20 µs typical. The power-good delay timing is common to all supply rails, but the power good comparators and outputs function independently.

7.4.1.8 Light-Load PFM Mode

An external clock or a high level on the SYNC pin or enabling Buck3 results in forced continuous-mode operation of the bucks. Having the SYNC pin low or open allows the buck controllers to operate in discontinuous mode at light loads by turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.

In discontinuous mode, as the load decreases, the duration of the clock period when both the high-side and the low-side MOSFETs are turned off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and V_IN > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1% of the set full-load current if the choice of the inductor and the sense resistor is appropriate as recommended in the slope compensation section.

Figure 19. Modes of Operation

In low-power PFM mode, the buck controllers monitor the V_SENSEx voltage and compare it with the 0.8 V internal reference. Whenever the V_SENSEx value falls below the reference, the high-side MOSFET turns on for a pulse-duration inversely proportional to the difference across VIN-S2 for Buck 1 and VIN-S4 for Buck2. At the end of this on-time, the high-side MOSFET turns off and the current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse occurs the next time V_SENSEx falls below the reference value. This results in a constant volt-second T_ON hysteretic operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and 35 µA when both channels are active.

As the load increases, the pulse become more and more frequent until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion for exit from the low-power mode is when VIN falls low enough to require a higher-than-80% duty cycle of the high-side MOSFET.

The TPS43340-Q1 can support the full-current load during low-power mode until the transition to normal mode takes place. The design ensures the low-power-mode exit occurs at 10% (typical) of full-load current if the inductor and sense resistor choices are as recommended. Moreover, there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.

In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for entry to low-power mode.