10.1 Layout Guidelines

Certain points must be considered before starting a layout work using the TPS51117.

• Connect the RC low-pass filter from 5-V supply to V5FILT, 300 Ω and 1 μF are recommended. Place the filter capacitor close to the device, within 12 mm (0.5 inches) if possible.
• Connect the overcurrent setting resistors from TRIP to GND close to the device, right next to the device, if possible. The trace from TRIP to resistor and resistor to GND should avoid coupling to a high-voltage switching node.
• The discharge path (VOUT) should have a dedicated trace to the output capacitor(s); separate from the output voltage sensing trace, and use a 1.5-mm (60 mils) or wider trace with no loops. Make sure the feedback current setting resistor (the resistor between VFB to GND) is tied close to the device GND. The trace from this resistor to the VFB pin should be short and thin. Place on the component side and avoid vias between this resistor and the device.
• Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use a 0.65-mm (25 mils) or wider trace.
• All sensitive analog traces and components such as VOUT, VFB, GND, EN_PSV, PGOOD, TRIP, V5FILT, and TON should be placed away from high-voltage switching nodes such as LL, DRVL, DRVH or VBST to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components.
• Gather the ground terminals of the V_IN capacitor(s), V_OUT capacitor(s), and the source of the low-side MOSFETs as close as possible. GND (signal ground) and PGND (power ground) should be connected strongly together near the device. The PCB trace defined as LL node, which connects to the source of the high-side MOSFET, the drain of the low-side MOSFET, and the high-voltage side of the inductor, should be as short and wide as possible.

10.2 Layout Example

Figure 26. Layout Recommendation

10.3 Thermal Considerations

Power dissipation of the TPS51117 is mainly generated from the FET drivers. Average drive current can be estimated by gate charge, Q_g, times the switching frequency.

Equation 14.

Q_g is the charge needed to charge gate capacitance up to the V5DRV voltage of 5 V. Actual values are shown on MOSFET datasheets provided by the manufacturer. Total power dissipation, therefore, to drive the top and bottom MOSFETs can be calculated by the following equation Equation 15.

Equation 15.

This power plus a small amount of dissipation (less than 5 mW) from controller circuitry needs to be effectively dissipated from the package. Maximum power dissipation allowed for the package is calculated by:

Equation 16.

where

• T_J(max) is 125°C.
• T_A(max) is the maximum ambient temperature in the system.
• R_θJA is the thermal resistance from the silicon junction to the ambient.

This thermal resistance strongly depends on board layout. The TPS51117 is assembled in a standard TSSOP package and the heat mainly moves to the board through its leads.