SLVS631C December 2005 – May 2015 TPS51117
The TPS51117 is a synchronous buck controller for POL voltage regulation in notebook PC applications. The controller is dedicated for the operation of the Adaptive On-Time D-CAP mode. This mode provides ease-of-use, low external component count, and fast transient response. Auto-skip mode for high efficiency down to the milliampere load range, or PWM-only mode for low-noise operation is selectable.
The TPS51117 employs an adaptive on-time control scheme and does not have a dedicated oscillator onboard. However, the device emulates a constant frequency by feed-forwarding the input and output voltages into the on-time one-shot timer. The ON time is controlled inverse proportional to the input voltage, and proportional to the output voltage, so that the duty ratio is kept as VOUT/VIN technically with the same cycle time. Equation 1 shows a simplified calculation of the ON time.
Here, RTON is the external resistor connected from TON pin to the LL node. In the equation, 19 pF represents the internal timing capacitor with some typical parasitic capacitance at the TON pin. Also, 50 ns is the turnoff delay time contributed by the internal circuit and that of the high-side MOSFET. Although this equation provides a good approximation with which to begin, the accuracy depends on each design and selection of the high-side MOSFET. Figure 19 shows the relationship of RTON to the switching frequency.
The TPS51117 does not have a pin connected to VIN, but the input voltage information comes from the switch node (LL node) during the ON-state. An advantage of LL monitoring is that the loss in the high-side NFET is now a part of the ON-time calculation, thereby making the frequency more stable with load.
Another consideration about frequency is jitter. Jitter may be caused by many reasons, but the constant on-time D-CAP mode scheme has some amount of inherent jitter. Because the output voltage ripple height is in the range of a couple of tens of millivolts. A millivolt order of noise on the feedback signal can affect the frequency by a few to ten percent. This is normal operation and has little harm to the power supply performance.
The low-side driver is designed to drive high-current, low RDS(on) N-channel MOSFETs. The drive capability is represented by its internal resistance, which is 5 Ω for V5DRV to DRVL and 1.5 Ω for DRVL to PGND. A dead time to prevent shoot-through is internally generated between high-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on. A 5-V bias voltage is delivered from V5DRV supply. The average drive current is calculated by the FET gate charge at Vgs = 5 V times the switching frequency. The instantaneous drive current is supplied by an input capacitor connected between V5DRV and GND.
The high-side driver is designed to drive high-current, low RDS(on) N-channel MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from V5DRV supply. An internal PN diode is connected between V5DRV to VBST. The designer can add an external Schottky diode if forward drop is critical to drive the high-side NFET or to achieve the last 1% efficiency improvement. The average drive current is also estimated by the gate charge at Vgs = 5 V times the switching frequency. The instantaneous drive current is supplied by the flying capacitor between the VBST pin and LL pin. The drive capability is represented by its internal resistance, which is 5 Ω for VBST to DRVH and 1.5 Ω for DRVH to LL.
The TPS51117 has an internal, 1.2-ms, voltage servo soft-start with overcurrent limit. When the EN_PSV pin becomes high, an internal DAC begins ramping up the reference voltage to the error amplifier. Smooth control of the output voltage is maintained during start-up.
The TPS51117 has powergood output. PGOOD is an open-drain 7.5-mA pulldown output. This pin should be typically connected to a 5-V power supply node through a 100-kΩ resistor. The powergood function is activated after the soft start has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect the power good state and the powergood signal becomes high after a 64-μs internal delay. If the output voltage goes outside ±10% of the target value, the powergood signal becomes low immediately.
The TPS51117 discharges output when EN_PSV is low or the converter is in a fault condition (UVP, OVP, UVLO, or thermal shutdown). The TPS51117 discharges output using an internal 20-Ω MOSFET, which is connected to VOUT and PGND. The discharge time-constant is a function of the output capacitance and resistance of the discharge transistor.
The TPS51117 has cycle-by-cycle overcurrent limiting control. Inductor current is monitored during the OFF-state and the controller keeps the OFF-state when inductor current is larger than the overcurrent trip level. To provide both good accuracy and a cost-effective solution, the TPS51117 supports temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor, RTRIP. The TRIP terminal sources 10-μA ITRIP current, and the trip level is set to the OCL trip voltage, VTRIP as in the following equation.
Inductor current is monitored by the voltage between the PGND pin and the LL pin so the LL pin should be connected to the drain terminal of the low-side MOSFET. ITRIP has 4500 ppm/°C temperature coefficient to compensate the temperature dependency of the RDS(on). PGND is used as the positive current sensing node so PGND should be connected to the source terminal of the bottom MOSFET.
As the comparison is done during the OFF-state, VTRIP sets the valley level of the inductor current. Thus, the load current at overcurrent threshold, Iocp, can be calculated as follows;
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output voltage tends to fall. Eventually, the output voltage crosses the undervoltage protection threshold and shutdown.
The TPS51117 also supports cycle-by-cycle negative overcurrent limiting in PWM-only mode. The overcurrent limit is set to be negative but is the same absolute value as the positive overcurrent limit. If output voltage continues to rise, the bottom MOSFET stays on, thus inductor current is reduced and reverses direction after it reaches zero. When there is too much negative current in the inductor, the bottom MOSFET is turned off and the current flows to VIN through the body diode of the top MOSFET. Because this protection reduces current to discharge the output capacitor, output voltage tends to rise, eventually hitting the overvoltage protection threshold and shutdown. To prevent false OVP from triggering, the bottom MOSFET is turned on again 400 ns after it is turned off. If the device hits the negative overcurrent threshold again before output voltage is discharged to the target level, the bottom MOSFET is turned off and the process repeats, which is called NOCL Buzz. The device ensures maximum allowable discharge capability when output voltage continues to rise. On the other hand, if the output voltage is discharged to the target level before the NOCL threshold is reached, the bottom MOSFET is turned off, the top MOSFET is then turned on, and the device resumes normal operation.
The TPS51117 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage condition. When the feedback voltage becomes higher than 115% of the target value, the top MOSFET is turned off and the bottom MOSFET is turned on immediately. The output is also discharged by the internal 20-Ω transistor. Also, the TPS51117 monitors VOUT terminal voltage directly and if it becomes greater than 5.75 V, it turns off the top MOSFET driver.
When the feedback voltage becomes lower than 70% of the target value, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 32 μs, the TPS51117 latches off the high-side and low-side MOSFETs and discharges the output with the internal 20-Ω transistor. This function is enabled after 2 ms from when EN_PSV is brought high, that is, UVP is disabled during start-up.
Referring to Figure 20 which shows the timing sequence, to ensure the proper start-up of the TPS51117, always ensure that VEN_PSV is less or equal to that of VV5FILT prior to VV5FILT reaching VUVLO.
The TPS51117 has V5FILT undervoltage lockout protection (UVLO). When the V5FILT voltage is lower than the UVLO threshold voltage, the TPS51117 is shut off. This is a nonlatched protection.
The TPS51117 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 160°C), the TPS51117 shuts itself off. Both top and bottom gate drivers are tied low with output discharged through the VOUT terminal. This is also a nonlatched protection. The device recovers once the temperature has decreased approximately 12°C.
The main control loop of the TPS51117 is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports proprietary D-CAP Mode that uses an internal compensation circuit and is suitable for minimal external component count configuration when an appropriate amount of ESR at the output capacitor(s) is allowed. Basic operation of D-CAP Mode can be described as follows.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON-state. This MOSFET is turned off, or becomes OFF-state, after the internal one-shot timer expires. This one-shot is determined by VIN and VOUT to keep the frequency fairly constant over the input voltage range at steady-state, hence it is called adaptive on-time control or fixed frequency emulated on-time control (see PWM Frequency and Adaptive On-Time Control). The MOSFET is turned on again when both feedback information, monitored at VFB voltage, indicates insufficient output voltage and inductor current information indicates below the overcurrent limit. Repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side or rectifying MOSFET is turned on each OFF-state to keep the conduction loss to a minimum.
The TPS51117 supports selectable PWM-only and auto-skip operation modes. If EN_PSV is grounded, the switching regulator is disabled. If the EN_PSV pin is connected to 3.3 V or 5 V, the regulator is enabled with auto-skip mode selected. The rectifying MOSFET is turned off when inductor current information detects zero level. This enables a seamless transition to reduced frequency operation during a light-load condition so that high efficiency is maintained over a broad range of load currents. If the EN_PSV pin is floated, it is internally pulled up to 1.95 V, and the regulator is enabled with PWM-only mode selected. The rectifying MOSFET is not turned off when inductor current reaches zero. The converter runs forced continuous conduction mode for the entire load range. System designers may want to use this mode to avoid a certain frequency during a light-load condition but with the cost of low efficiency. However, be aware the output has the capability to both source and sink current in this mode. If the output terminal is connected to a voltage source higher than the target of the regulator, the converter sinks current from the output and boosts the charge into the input capacitor. This may cause unexpected high voltage at VIN and may damage the power FETs.
If auto-skip mode is selected, the TPS51117 automatically reduces the switching frequency during a light-load condition to maintain high efficiency. This reduction of frequency is achieved smoothly and without an increase of Vout ripple or load regulation. Detailed operation is described as follows. As the output current decreases from a heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. Because the output voltage is still higher than the reference at this moment, both high-side and low-side MOSFETs are turned off and wait for the next cycle. As the load current decreases further, the converter runs in discontinuous conduction mode, taking longer time to discharge the output capacitor below the reference voltage. The ON time is kept the same as during the heavy load condition. In reverse, when the output current increases from a light load to a heavy load, the switching frequency increases to the preset value as the inductor current reaches to the continuous conduction. The transition load point to light-load operation, IOUT(LL) (that is, the threshold between continuous and discontinuous conduction mode), can be calculated as follows:
Switching frequency versus output current in the light-load condition is a function of L, fsw, VIN and VOUT, but it decreases almost proportional to the output current from the IOUT(LL) given in Equation 5. For example, it is about 60 kHz at IOUT(LL)/5 if the PWM switching frequency is 300 kHz.