SLVSAE6A July   2010  – August 2014 TPS53129

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematics
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
  8. Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 PWM Operation
      2. 9.3.2 Light-Load Condition
      3. 9.3.3 Drivers
      4. 9.3.4 PWM Frequency and Adaptive On-Time Control
      5. 9.3.5 5-Volt Regulator
      6. 9.3.6 Soft Start
      7. 9.3.7 Pre-Bias Support
    4. 9.4 Device Functional Modes
      1. 9.4.1 Output Discharge Control
      2. 9.4.2 Over Current Limit
      3. 9.4.3 Over/Under Voltage Protection
      4. 9.4.4 UVLO Protection
      5. 9.4.5 Thermal Shutdown
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Typical Application Circuits
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
      4. 10.2.4 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Suggestions
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • D-CAP2™ Mode Control
    • Fast Transient Response
    • No External Parts Required for Loop Compensation
    • Compatible With Ceramic Output Capacitors
  • High Initial Reference Accuracy (±1%)
  • Low Output Ripple
  • Wide Input Voltage Range: 4.5 V to 24 V
  • Output Voltage Range: 0.76 V to 5.5 V
  • Low-Side RDS(ON) Loss-Less Current Sensing
  • Adaptive Gate Drivers with Integrated Boost Diode
  • Adjustable Soft Start
  • Non-Sinking Pre-Biased Soft Start
  • 700-kHz Switching Frequency
  • Cycle-by-Cycle Over-Current Limiting Control
  • 30-mV to 300-mV OCP Threshold Voltage
  • Thermally Compensated OCP by 4000 ppm/°C at ITRIP
  • Auto-Skip Eco-mode™ for High Efficiency at Light Load

2 Applications

  • Point-of-Load Regulation in Low Power Systems for Wide Range of Applications
    • Digital TV Power Supply
    • Networking Home Terminal
    • Digital Set-Top Box (STB)
    • DVD Player/Recorder
    • Gaming Consoles

3 Description

The TPS53129 is a dual, adaptive on-time D-CAP2™ mode synchronous buck controller. The TPS53129 enables system designers to complete the suite of various end equipment’s power bus regulators with cost effective, low component count, and low standby current solution. The main control loop for the TPS53129 uses the D-CAP2™ mode control which provides a very fast transient response with no external components. The TPS53129 also has a circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR, ceramic capacitors. The fixed frequency emulated adaptive on-time control supports seamless operation between PWM mode at heavy load condition and reduced frequency operation at light load for high efficiency down to milliampere range.The device provides convenient and efficient operation with input voltages from 4.5 V to 24 V and output voltages from 0.76 V to 5.5 V.

The TPS53129 is available in 4-mm x 4-mm 24-pin QFN (RGE) or 24-pin TSSOP (PW) packages, and is specified from -40°C to 85°C ambient temperature range.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS53129 VQFN (24) 4.00 mm x 4.00 mm
TSSOP (24) 4.40 mm x 7.80 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematics

TPS53129 qfn4_lvsae6.gif
TPS53129 tssop1_lvsae6.gif