SLUSAE5G August 2011 – April 2021 TPS53355
TPS53355 provides an internal 5-V LDO function using input from VDD and output to VREG. When the VDD voltage rises above 2 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG voltage provides the bias voltage for the internal analog circuitry and also provides the supply voltage for the gate drives.
The 5-V LDO is controlled by the EN pin. The LDO starts-up any time VDD rises to approximately 2 V. Figure 7-1