SLUSFF0 September   2023 TPS536C9T

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Device and Documentation Support
    1. 5.1 Documentation Support
    2. 5.2 Receiving Notification of Documentation Updates
    3. 5.3 Support Resources
    4. 5.4 Trademarks
    5. 5.5 Electrostatic Discharge Caution
    6. 5.6 Glossary
  7. 6Mechanical, Packaging, and Orderable Information
    1. 6.1 Package Option Addendum
    2. 6.2 Packaging Information
    3. 6.3 Tape and Reel Information
  8. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Description

The TPS536C9T is a VR14 SVID compliant step down controller with trans-inductor voltage regulator (TLVR) topology support, two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI smart power stages. Advanced control features such as the D-CAP+ architecture provide fast transient response, low output capacitance, and good dynamic current sharing. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TPS536C9T RSL (QFN, 48) 6.00 mm × 6.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.
The package size (length × width) is a nominal value and includes pins, where applicable.
Device Information
PART NUMBER(1) PHASE COUNT
TPS536C9T 12 phases
See the Device Comparison Table
GUID-20210714-CA0I-NZJM-T7DK-V1MCGHPGSWNQ-low.svg Simplified Application (Interleaved TLVR)