SLUSFF0A September   2023  – July 2025 TPS536C9T

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Device and Documentation Support
    1. 4.1 Documentation Support
    2. 4.2 Receiving Notification of Documentation Updates
    3. 4.3 Support Resources
    4. 4.4 Trademarks
    5. 4.5 Electrostatic Discharge Caution
    6. 4.6 Glossary
  6. 5Mechanical, Packaging, and Orderable Information
  7. 6Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Input voltage range: 4.5V to 17V
  • Output voltage range: 0.25V to 5.5V
  • Dual output supporting N+M phase configurations (N+M ≤ 12, M ≤ 6)
  • Fully compatible with TI smart power stages
  • Supports voltage- and current-source Imon power stages, with internal 1kΩ resistor
  • Supports dual side power delivery with 12"+ trace length
  • Intel® VR14 SVID compliant with PSYS support
  • Backward compatible to VR13.HC/VR13.0 SVID
  • Automatic NVM fault status logging
  • Enhanced D-CAP+ control to provider superior transient performance with excellent dynamic current sharing
  • Dynamic phase shedding with programmable thresholds for optimizing efficiency at light and heavy loads
  • Configurable with non-volatile memory (NVM) for low external component count
  • Individual per-phase IMON calibration, with multi-slope gain calibration to increase system accuracy
  • Diode braking with programmable timeout for reduced transient overshoot
  • Programmable per-phase valley current limit (OCL)
  • PMBus® v1.3.1 system interface for telemetry of voltage, current, power, temperature, and fault conditions
  • New soft-shutdown option for overvoltage fault
  • Programmable loop compensation through PMBus
  • 6.00mm × 6.00mm, 48-pin, QFN package