SLVSAA6B April   2010  – November 2014 TPS54240

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-Mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Adjusting The Output Voltage
      8. 7.3.8  Enable And Adjusting Undervoltage Lockout
      9. 7.3.9  Slow-Start / Tracking Pin (SS/TR)
      10. 7.3.10 Overload Recovery Circuit
      11. 7.3.11 Sequencing
      12. 7.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      13. 7.3.13 Overcurrent Protection and Frequency Shift
      14. 7.3.14 Selecting the Switching Frequency
      15. 7.3.15 How to Interface to RT/CLK Pin
      16. 7.3.16 Powergood (PWRGD Pin)
      17. 7.3.17 Overvoltage Transient Protection
      18. 7.3.18 Thermal Shutdown
      19. 7.3.19 Small Signal Model for Loop Response
      20. 7.3.20 Simple Small Signal Model for Peak Current Mode Control
      21. 7.3.21 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum VIN (V(VIN) = < 3.5 V)
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 TPS54240 3.3-V Output Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Selecting the Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection (LO)
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Catch Diode
          5. 8.2.1.2.5  Input Capacitor
          6. 8.2.1.2.6  Slow-Start Capacitor
          7. 8.2.1.2.7  Bootstrap Capacitor Selection
          8. 8.2.1.2.8  Undervoltage Lock Out Set Point
          9. 8.2.1.2.9  Output Voltage And Feedback Resistors Selection
          10. 8.2.1.2.10 Compensation
          11. 8.2.1.2.11 Discontinuous Mode And Eco-Mode Boundary
          12. 8.2.1.2.12 Power Dissipation Estimate
        3. 8.2.1.3 Application Curves
      2. 8.2.2 TPS54240 Inverting Power Supply
      3. 8.2.3 TPS54240 Split Rail Power Supply
      4. 8.2.4 12-V To 3.8-V GSM Power Supply
      5. 8.2.5 24-V to 4.2-V GSM Power Supply
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage VIN –0.3 47 V
EN –0.3 5
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT-PH 8 V
PH –0.6 47
PH, 10-ns Transient –2 47
Voltage difference PAD to GND ±200 mV
Source current EN 100 μA
BOOT 100 mA
VSENSE 10 μA
PH Current Limit A
RT/CLK 100 μA
Sink current VIN Current Limit A
COMP 100 μA
PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) -2 2 kV
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) -500 500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating Input Voltage on (VIN pin) 3.5 42 V
Operating junction temperature, TJ -40 150 °C

6.4 Thermal Information

THERMAL METRIC(1)(2)(2) TPS54240 UNIT
DGQ DRC
10 PINS 10 PINS
θJA Junction-to-ambient thermal resistance (standard board) 62.5 40 °C/W
ψJT Junction-to-top characterization parameter 1.7 0.6
ψJB Junction-to-board characterization parameter 20.1 7.5
θJCtop Junction-to-case(top) thermal resistance 83 65
θJCbot Junction-to-case(bottom) thermal resistance 21 7.8
θJB Junction-to-board thermal resistance 28 8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 42 V
Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V 1.3 4 μA
Operating : nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C 138 200
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 1.15 1.25 1.36 V
Input current Enable threshold +50 mV –3.8 μA
Enable threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
Voltage reference TJ = 25°C 0.792 0.8 0.808 V
0.784 0.8 0.816
HIGH-SIDE MOSFET
On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 mΩ
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER (EA)
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 310 μS
Error amplifier transconductance (gM) during slow start –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V		 70 μS
Error amplifier dc gain VVSENSE = 0.8 V 10,000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±27 μA
COMP to switch current transconductance 10.5 A/V
CURRENT LIMIT
Current limit threshold VIN = 12 V, TJ = 25°C 3.5 6.1 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching Frequency Range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 581 720 kHz
Switching Frequency Range using CLK mode 300 2200 kHz
Minimum CLK input pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock in time Measured at 500 kHz 100 μs
SLOW-START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.15 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 382 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWERGOOD (PWRGD PIN)
VVSENSE VSENSE threshold VSENSE falling 92%
VSENSE rising 94%
VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, I(PWRGD) = 100 μA 0.95 1.5 V

6.6 Typical Characteristics

C001_SLVS919.gif
Figure 1. On Resistance vs Junction Temperature
imax_tj_lvsa86.gifFigure 3. Switch Current Limit vs Junction Temperature
C005_SLVS919.gif
VI = 12 V TJ = 25°C
Figure 5. Switching Frequency vs RT/CLK Resistance High Frequency Range
ea_tj_lvsa86.gif
Figure 7. EA Transconductance during Slow Start vs Junction Temperature
C009_SLVS919.gif
VI = 12 V
Figure 9. EN Pin Voltage vs Junction Temperature
C011_SLVS919.gif
VI = 12 V VI(EN) = Threshold +50 mV
Figure 11. EN Pin Current vs Junction Temperature
ss_tr2_tj_lvsa86.gif
Figure 13. SS/TR Discharge Current vs Junction Temperature
C015_SLVS919.gif
VI = 12 V
Figure 15. Shutdown Supply Current vs Junction Temperature
icc2_tj_lva86.gif
Figure 17. VIN Supply Current vs Junction Temperature
C019_SLVS919.gif
VI = 12 V
Figure 19. PWRGD on Resistance vs Junction Temperature
C021_SLVS919.gifFigure 21. BOOT-PH UVLO vs Junction Temperature
offset_vs_lva86.gifFigure 23. SS/TR to VSENSE Offset vs Vsense
C002_SLVS919.gif
VI = 12 V
Figure 2. Voltage Reference vs Junction Temperature
C004_SLVS919.gif
VI = 12 V RT = 200 kΩ
Figure 4. Switching Frequency vs Junction Temperature
C006_SLVS919.gif
VI = 12 V TJ = 25°C
Figure 6. Switching Frequency vs RT/CLK Resistance Low Frequency Range
ea2_tj_lvsa86.gif
Figure 8. EA Transconductance vs Junction Temperature
C010_SLVS919.gif
VI = 12 V VI(EN) = Threshold +50 mV
Figure 10. EN Pin Current vs Junction Temperature
C012_SLVS919.gif
VI = 12 V
Figure 12. SS/TR Charge Current vs Junction Temperature
C014_SLVS919.gif
VI = 12 V TJ = 25°C
Figure 14. Switching Frequency vs VSENSE
icc_vi_lvs918.gif
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
icc_vi2_lvsaa6.gif
Figure 18. VIN Supply Current vs Input Voltage
C020_SLVS919.gif
VI = 12 V
Figure 20. PWRGD Threshold vs Junction Temperature
C022_SLVS919.gifFigure 22. Input Voltage UVLO vs Junction Temperature
offset_tj_lvsa86.gifFigure 24. SS/TR to VSENSE Offset vs Temperature