SLUSB69B May 2014 – July 2016 TPS544B20 , TPS544C20
PRODUCTION DATA.
The TPS544B20 and TPS544C20 devices are highly-integrated synchronous step-down DC-DC converters. These devices are used to convert a higher DC input voltage to a lower DC output voltage, with a maximum output current of 20 A and 30 A respectively.
Use the following design procedure to select key component values for this family of devices, and set the appropriate behavioral options according to the PMBus protocol.
For this design example, use the following input parameters.
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
V_{I} | Input voltage | 4.5 | 12.0 | 18.0 | V | |
V_{I(ripple)} | Input ripple voltage | I_{OUT} = 30 A | 0.4 | V | ||
V_{O} | Output voltage | 1.8 | V | |||
Line regulation | 4.5 V ≤ V_{I} ≤ 18 V | 0.5% | ||||
Load regulation | 0 V ≤ I_{O} ≤ 30 A | 0.5% | ||||
V_{(PP)} | Output ripple voltage | I_{O} = 30 A | 18 | mV | ||
V_{(OVER)} | Transient response overshoot | I_{(STEP)} = 10 A | 36 | mV | ||
V_{(UNDER)} | Transient response undershoot | I_{(STEP)} = 10 A | -36 | mV | ||
I_{O} | Output current | 5 V ≤ V_{I} ≤ 18 V | 0 | 20 | 30 | A |
t_{SS} | Soft-start time | V_{I} = 12 V | 2.7 | ms | ||
I_{OC} | Overcurrent trip point | 40 | A | |||
η | Efficiency | I_{O} = 20 A, V_{I} = 12 V | 90% | |||
f_{SW} | Switching frequency | 500 | kHz |
There is a trade-off between higher and lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher switching frequency produce higher switch losses, which decrease efficiency and impact thermal performance. In this design, a moderate switching frequency of 500 kHz achieves both a balance between a small solution size and high-efficiency operation. With the frequency selected, use Table 2 to select the timing resistor. For a frequency of 500 kHz R_{RT} is 38.2 kΩ.
To calculate the value of the output inductor, use Equation 12. The coefficient K_{IND} represents the amount of peak-to-peak inductor ripple current relative to the maximum output current. The output capacitor filters the inductor ripple current; therefore, choosing a high inductor ripple current impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. To achieve balanced performance, maintain a K_{IND} coefficient between 0.3 and 0.4. Using this target ripple current, the required inductor size can be calculated as shown in Equation 12.
Selecting K_{IND} = 0.3, the target inductance L_{1 }= 360 nH. Using the next standard value, the 320 nH Pulse (brand) PG077.321NL is chosen in this application for its high current rating, low DCR, and small size. The inductor ripple current, RMS current, and peak current can be calculated using Equation 13, Equation 14 and Equation 15. These values should be used to select an inductor with approximately the target inductance value, and current ratings that allow normal operation with some margin.
The Pulse PG077.321NL is rated for 45 A RMS current, and 48-A saturation. Using this inductor, the ripple current I_{RIPPLE}= 10.1 A, the RMS inductor current I_{L(rms)}= 30.14 A, and peak inductor current I_{L(peak)}= 35 A.
There are three primary considerations for selecting the value of the output capacitor. The output capacitor affects three criteria:
The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a load transition is the first criterion. The output capacitor must supply the load with the required current when not immediately provided by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects the magnitude of voltage deviation during the transient.
These devices use Adaptive Constant On-Time (COT) control. During a transient, the ON-time remains unchanged from normal operation, but the off-time shortens to allow a rapid increase in the inductor current in order to meet the demands of the load transition. To estimate the time required to respond to a load increase, calculate the number of switching cycles required to change the inductor current using Equation 16.
And estimate the time needed to produce that number of cycles during a transient as Equation 17:
The output capacitor must support the full change in output current for half of the time, so the minimum output capacitance can be estimated by Equation 18:
The output capacitor must also absorb the full change in output current for half of the time needed to remove the excess current from the inductor during a rapid load decrease. This minimum output capacitance can be estimated using Equation 19:
In order to meet the transient response requirements, the output capacitance must be greater than the larger of C_{undershoot} and C_{overshoot}.
In this case, the highest minimum output capacitance (C_{OUT(min)}) to meet the response to a load transition is the overshoot requirement, which dictates the minimum output capacitance. Therefore, using Equation 19, the minimum output capacitance required to meet the transient requirement is 494 µF.
The output voltage ripple is the second criterion. Equation 20 calculates the minimum output capacitance required to meet the output voltage ripple specification. This criterion is the requirement when the impedance of the output capacitance is dominated by ESR.
In this case, the maximum output voltage ripple is 18 mV. Under this requirement, the minimum output capacitance for ripple (as calculated in Equation 20) yields 140 μF. Because this capacitance value is smaller than the output capacitance required to meet the transient response, select the output capacitance value based on the transient requirement. For this application, two 220-µF, low-ESR polymer bulk capacitors, three 47-µF capacitors and three 22-µF ceramic capacitors are selected to meet the transient specification with at least 80% margin. Therefore C_{OUT} equals 647 µF.
With the target output capacitance value chosen, Equation 21 calculates the maximum ESR the output capacitor bank can have to meet the output voltage ripple specification. Equation 21 indicates the ESR should be less than 1.4 mΩ. The six ceramic capacitors each contribute approximately 2 mΩ, making the effective ESR of the output capacitor bank approximately 0.33 mΩ, meeting the specification with sufficient margin.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in, which increases the minimum required capacitance value. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (root mean square) value of the maximum ripple current. Equation 22 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 22 yields 2.28 A.
D-CAP mode control requires that the ESR ripple at the FB pin be at least 15 mV (or 2.5%) of the output voltage and the ESR-zero frequency of the output capacitor is less than 1/4 the switching frequency. Because this design requires output voltage ripple less than 2.5% of the output voltage and uses low-ESR, specialty polymer, and ceramic output capacitors, this design uses D-CAP2 mode control. Because D-CAP2 mode control uses an internally generated ramp to emulate the ESR of the output capacitor, D-CAP2 mode requires sufficient output capacitance to maintain an effective ESR-zero frequency less than 1/4 of the nominal switching frequency with this emulated ESR. The minimum capacitance for stability can be calculated in Equation 23 using τ_{Iem} from Table 11:
NOMINAL FREQUENCY (kHz) | τ_{Iem}(µs) |
---|---|
250 | 104 |
300 | 98 |
400 | 87 |
500 | 76 |
650 | 60 |
750 | 52 |
850 | 44 |
1000 | 33 |
The TPS544B20 and TPS544C20 devices require a capacitor with these features:
The power stage input decoupling capacitance (effective capacitance at the VIN and GND pins) must be sufficient to supply the high switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple to the device during full load. The input ripple current can be calculated using Equation 24.
The minimum input capacitance and ESR values for a given input voltage ripple specification, V_{IN(ripple)}, are shown in Equation 25 and Equation 26. The input ripple is composed of a capacitive portion, V_{RIPPLE(cap)}, and a resistive portion, V_{RIPPLE(esr)}.
The value of a ceramic capacitor varies significantly with temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectric capacitors are usually selected for power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable during temperature changes. The input capacitor must also be selected with the DC bias taken into account. To support the maximum input voltage, this design requires a ceramic capacitor with a rating of at least 25 V. Allow 0.1-V input ripple for V_{RIPPLE(cap)}, and 0.3-V input ripple for V_{RIPPLE(esr)}. Using Equation 25 and Equation 26, the minimum input capacitance for this design is 60 µF, and the maximum ESR is 2.8 mΩ. Four 22-μF, 25-V ceramic capacitors and two additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for the power stage. For the VDD pin, one 1.0-μF, 25-V ceramic capacitor was selected. The input voltage (VIN) and power input voltage (PVIN) pins must be tied together. The input capacitance value determines the input ripple voltage of the regulator. Using the design example values, I_{OUT(max)} = 30 A, C_{IN} = 288 μF, f_{SW} = 500 kHz, yields a maximum RMS input ripple current of 14.7 Arms.
A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have voltage rating of 25 V or higher. To reduce the dV/dt of the rising edge of the SW node, reduce ringing and EMI, a resistor R_{BOOT} up to 5 Ω can be placed in series with the bootstrap capacitor.
This design does not include an auxiliary 5-V supply, so BPEXT is terminated to GND. According to the recommendations in , BP3 is bypassed to AGND with 100 nF of capacitance, and BP6 is bypassed to GND with 4.7-µF of capacitance. In order for the regulator to function properly, it is important that these capacitors be located close to the TPS544C20, with low-impedance return paths to AGND or GND as appropriate. See Figure 45 for more information.
Although it is possible to operate the TPS544C20 within absolute maximum ratings without including any ringing reduction techniques, some designs may require external components to further reduce ringing levels. This example uses two approaches:
Including a high-frequency bypass capacitor is a lossless ringing reduction technique which helps minimizes the outboard parasitic inductances in the power stage. These capacitors store energy during the low-side MOSFET on-time, and discharge once the high-side MOSFET is turned on. For this example a 4.7-nF, 25-V, 0402 sized high-frequency capacitor is selected. The placement of this capacitor (shown in Figure 46) is critical to its effectiveness.
Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF capacitor and a 3-Ω resistor are chosen. In this example an 0805 resistor is chosen, which is rated for 0.125 W, nearly twice the estimated power dissipation. Figure 33 and Figure 34 show the effect of the R-C snubber on the rising edge of the SW pin. See SLUP100 for more information about snubber circuits.
V_{IN} = 12 V | I_{OUT} = 20 A | Snubber = 1nF + 3Ω |
V_{IN} = 12 V | I_{OUT} = 20 A | Snubber = Open |
This application design uses a surface-mount MMBT3904SL for the temperature sensor, Q_{T}. In this example, the sensor monitors the PCB temperature where it is generally the highest, next to the power inductor. Placement of the temperature sensor and routing back to the TSNS pin are critical design features to reduce noise its temperature measurements. In this example, the temperature sensor is placed on the V_{OUT} side of the power inductor to avoid switching noise from the SW plane, and routed back to the TSNS and AGND pin. Additionally, a 330-pF capacitor, C_{T}, is placed from TSNS to AGND near the TSNS pin.
Disable external temperature sensing by terminating TSNS to AGND with a 0-Ω resistor. This termination forces the temperature readings to –40 °C, and prevents external over-temperature fault trips.
Several of the key design parameters for the TPS544B20 and TPS544C20 device can be configured according to the PMBus protocol, and stored to its non-volatile memory (NVM) for future use.
Use the ON_OFF_CONFIG (02h) command to select the turn-on behavior of the converter. For this example, the CNTL pin was used to enable or disable the converter, regardless of the state of OPERATION (01h), as long as input voltage is present, and above the UVLO threshold.
The minimum input voltage, V_{IN(min)} , for this example is 4.5 V. The VIN_ON command was set to 4.25 V, and the VIN_OFF command was set to 4.0 V, giving 250 mV of hysteresis. If VIN falls below VIN_OFF, power conversion stops, until it is raised above VIN_ON.
This example lacks specific turn-on or turn-off delay requirements, so SEQUENCE_TON_TOFF_DELAY was used to set both the turn-on and turn-off delays to 0 × the soft-start time, the delay between enabling power conversion, and the rise of the output voltage is approximately 400 µs. See the Soft-Start section for more information.
The TON_RISE command sets the soft-start time. When selecting the soft-start time, consider the charging current for the output capacitors. In some applications (for example those with large amounts of output capacitance) this current can lead to problems with nuisance tripping of the overcurrent protection circuitry. To avoid nuisance tripping, the output capacitor charging current should be included when choosing a soft-start time, and overcurrent threshold. The capacitor charging current can be calculated using Equation 27.
After calculating the charging current, the overcurrent threshold can then be calibrated to the sum of the maximum load current and the output capacitor charging current plus some margin.
In this example, the soft-start time is arbitrarily selected to be the default value, 2.7 ms. In this case, the charging current, I_{CAP} = 337 mA.
The IOUT_OC_FAULT_LIMIT command sets the overcurrent threshold. The current limit should be set to the maximum load current, plus the output capacitor charging current during start-up, plus some margin for load transitions and component variation. The amount of margin required depends on the individual application, but a suggested starting point is 30%. More or less may be required. For this application, the maximum load current is 30 A, the output capacitor charging current is 337 mA. This design uses the factory default overcurrent threshold of 39 A.
The IOUT_OC_FAULT_RESPONSE command sets the desired response to an overcurrent event. In this example, the converter is configured to latch-off in the event of an overcurrent. TPS544C20 device can also be configured to hiccup, (continuously restart waiting for a 7 x soft-start time-out between re-trials. )
The PCT_VOUT_FAULT_PG_LIMIT command configures the PGOOD, and regulation windows. This example includes a moderate threshold setting. The resulting power good window is ±12.5%, and the resulting overvoltage and undervoltage window is ±16.8%. More or less aggressive protection levels can be selected according to the PMBus protocol.
A feedback divider from DIFFO to AGND sets the output voltage. This design arbitrarily selects an R1 value of 20 kΩ. Using R1 and the desired output voltage, and calculate R_{BIAS } using Equation 28 to be 10 kΩ.
The TPS544B20 and TPS544C20 devices use D-CAP2 mode control with a transconductance error amplifier to eliminate the output voltage error introduced by valley voltage regulation. To stabilize the error amplifer, TI recommends a 10-nF capacitor from COMP to AGND. To improve transient response and increase phase margin, a series resistor, R_{COMP}, can be added. When using R_{COMP}, add a 1.0-nF capacitor from COMP to AGND to limit the error amplifier gain at high frequency. Use Equation 29 to calculate the value of R_{COMP}.
Alternatively, for output voltages 1.2 V and higher, a feedforward capacitor, C1, can be added in parallel with R1 from DIFFO to FB to provide similar improvement to transient response and phase margin. Use Equation 30 to calculate the value of C1.
The resulting design example frequency compensation values are:
V_{IN} = 5 V | f_{SW} = 500 kHz | T_{A} = 25 °C |
L = 410 nH | Snubber = Open | R_{BOOT} = 0 Ω |
R_{DCR} = 0.3 mΩ |
V_{IN} = 12 V |
V_{IN} = 12 V | I_{OUT} = 20 A |
V_{IN} = 12 V | I_{OUT} = 20 A | t_{FALL} = 2.0 µs |
V_{IN} = 12 V | I_{OUT} = 0 A | V_{PRE-BIAS}= 900 mV |
V_{IN} = 12 V | f_{SW} = 500 kHz | T_{A} = 25 °C |
L = 410 nH | Snubber = Open | R_{BOOT} = 0 Ω |
R_{DCR} = 0.3 mΩ |
V_{IN} = 12 V | I_{OUT} = 20 A |
V_{IN} = 12 V | I_{OUT} = 20 A | t_{RISE} = 2.0 µs |
V_{IN} = 12 V | I_{OUT} = 20 A |
Natural Convection | ||
V_{IN} = 12 V | I_{OUT} = 20 A | f_{SW} = 500 kHz |