10.1 Layout Guidelines

Layout is a critical portion of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. See Figure 72 for a PCB layout example.

• To reduce parasitic effects, bypass the V_DD pin to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric.
• Take care to minimize the loop area formed by the bypass capacitor connections, the V_DD pin, and the anode of the catch diode. Route the SW pin to the cathode of the catch diode and to the output inductor. Because the SW connection is the switching node, locate the catch diode and output inductor close to the SW pins, and minimize the area of the PCB conductor to prevent excessive capacitive coupling.
• Tie the GND pin directly to the copper pad under the IC for the exposed thermal pad. Connect this copper pad to internal PCB ground planes using multiple vias directly under the IC.
• For operation at full-rated load, the top-side ground area must provide adequate heat dissipating area.
• The RT/CLK pin is sensitive to noise, so locate the RT resistor as close as possible to the IC and route conductors with minimal lengths of trace.
• Figure 72 shows the approximate placement for the additional external components.
• It may be possible to obtain acceptable performance with alternate PCB layouts. However, this layout, meant as a guideline, demonstrably produces good results.

Boxing in the components in the design of Figure 46, the estimated printed-circuit board area is 1.025 in² (661 mm²). This area does not include test points or connectors. To further reduce the area, use a two-sided assembly and replace the 0603-sized passives with a smaller-sized equivalent.

10.2 Layout Example

Figure 72. PCB Layout Example