SLVSC60A September   2014  – January 2017 TPS54561-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse-Skipping Eco-mode Control Scheme
      4. 7.3.4  Low-Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjust Undervoltage Lockout
      8. 7.3.8  Soft-Start and Tracking Pin (SS/TR)
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Accurate Current-Limit Operation and Maximum Switching Frequency
      12. 7.3.12 Synchronization to RT/CLK Pin
      13. 7.3.13 Power Good (PWRGD Pin)
      14. 7.3.14 Overvoltage Protection
      15. 7.3.15 Thermal Shutdown
      16. 7.3.16 Small-Signal Model for Loop Response
      17. 7.3.17 Simplified Small-Signal Model for Peak-Current-Mode Control
      18. 7.3.18 Small-Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VI = < 4.5 V (Minimum VDD)
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection (L(O))
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Catch Diode
        6. 8.2.2.6  Input Capacitor
        7. 8.2.2.7  Soft-Start Capacitor
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  Undervoltage Lockout Set Point
        10. 8.2.2.10 Output Voltage and Feedback Resistor Selection
        11. 8.2.2.11 Compensation
        12. 8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
        13. 8.2.2.13 Power Dissipation Estimate
      3. 8.2.3 Safe Operating Area
      4. 8.2.4 Application Curves
      5. 8.2.5 Inverting Power Supply
      6. 8.2.6 Split-Rail Power Supply
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Custom Design with WEBENCH® Tools
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DPR Package
10-Pin WSON
(Top View)
TPS54561-Q1 DPR-10_PinOut_SLVSC60.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT 1 O The device requires a bootstrap capacitor between BOOT and SW. If the voltage on this capacitor is below the minimum required voltage to operate the high-side MOSFET, the gate driver switches off until the bootstrap capacitor recharges.
COMP 7 O Error amplifier output, and input to the output switch-current comparator (PWM comparator). Connect frequency compensation components to this pin.
EN 3 I Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjust Undervoltage Lockout section.
FB 6 I Inverting input of the transconductance (gm) error amplifier.
GND 8 — Ground
PWRGD 10 O Power-good is an open-drain output that asserts if the output voltage is low because of thermal shutdown, dropout, overvoltage, or EN shutdown.
RT/CLK 5 I Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. When pulled above the PLL upper threshold, a mode change occurs, and the pin becomes a synchronization input. This change disables the internal amplifier, and the pin is a high-impedance clock input to the internal PLL. Stopping the clocking edges re-enables the internal amplifier, and the operating mode returns to resistor programmed mode.
SS/TR 4 I Soft-start and tracking input pin. An external capacitor connected to this pin sets the output rise time. A voltage on this pin overrides the internal reference, which allows use of the pin for tracking and sequencing.
SW 9 I The source of the internal high-side power MOSFET, and switching node of the converter.
VDD 2 I Input supply pin with 4.5-V to 60-V operating range.
Thermal pad — — To ensure proper operation, electrically connect the GND pin to the copper pad under the IC on the printed circuit board.