SLUSCE4A January   2017  – July 2017 TPS548B22


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 25-A FET
      2. 7.3.2 On-Resistance
      3. 7.3.3 Package Size, Efficiency and Thermal Performance
      4. 7.3.4 Soft-Start Operation
      5. 7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
      6. 7.3.6 EN_UVLO Pin Functionality
      7. 7.3.7 Fault Protections
        1. Current Limit (ILIM) Functionality
        2. Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
        3. Out-of-Bounds Operation
        4. Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 DCAP3 Control Topology
      2. 7.4.2 DCAP Control Topology
    5. 7.5 Programming
      1. 7.5.1 Programmable Pin-Strap Settings
        1. Frequency Selection (FSEL) Pin
        2. VSEL Pin
        3. DCAP3 Control and Mode Selection
        4. Application Workaround to Support 4-ms and 8-ms SS Settings
      2. 7.5.2 Programmable Analog Configurations
        1. RSP/RSN Remote Sensing Functionality
          1. Output Differential Remote Sensing Amplifier
        2. Power Good (PGOOD Pin) Functionality
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS548B22 1.5-V to 18-V Input, 1-V Output, 25-A Converter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Design Procedure
        1.  Switching Frequency Selection
        2.  Inductor Selection
        3.  Output Capacitor Selection
          1. Minimum Output Capacitance to Ensure Stability
          2. Response to a Load Transient
          3. Output Voltage Ripple
        4.  Input Capacitor Selection
        5.  Bootstrap Capacitor Selection
        6.  BP Pin
        7.  R-C Snubber and VIN Pin High-Frequency Bypass
        8.  Optimize Reference Voltage (VSEL)
        9.  MODE Pin Selection
        10. Overcurrent Limit Design.
      4. 8.2.4 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVF|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

Consider these layout guidelines before starting a layout work using TPS548B22.

  • It is absolutely critical that all GND pins, including AGND (pin 30), DRGND (pin 29), and PGND (pins 13, 14, 15, 16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or plane.
  • Include as many thermal vias as possible to support a 25-A thermal operation. For example, a total of 35 thermal vias are used (outer diameter of 20 mil) in the TPS548B22EVM-847 available for purchase at (SLUUBE4)
  • Place the power components (including input/output capacitors, output inductor and TPS548B22 device) on one side of the PCB (solder side). Insert at least two inner layers (or planes) connected to the power ground, in order to shield and isolate the small signal traces from noisy power lines.
  • Place the VIN pin decoupling capacitors as close as possible to the PVIN and PGND pins to minimize the input AC current loop. Place a high-frequency decoupling capacitor (with a value between 1 nF and 0.1 µF) as close to the PVIN pin and PGND pin as the spacing rule allows. This placement helps surpress the switch node ringing.
  • Place VDD and BP decoupling capacitors as close as possible to the device pins. Do not use PVIN plane connection for the VDD pin. Separate the VDD signal from the PVIN signal by using separate trace connections. Provide GND vias for each decoupling capacitor and make the loop as small as possible.
  • Ensure that the PCB trace defined as switch node (which connects the SW pins and up-stream of the output inductor) are as short and wide as possible. In the TPS548B22EVM-847 design, the SW trace width is 200 mil. Use a separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine these connections.
  • Place all sensitive analog traces and components (including VOSNS, RSP, RSN, ILIM, MODE, VSEL and FSEL) far away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise coupling. In addition, place MODE, VSEL and FSEL programming resistors near the device pins.
  • The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion. Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit uses the VOSNS pin for on-time adjustment. It is critical to tie the VOSNS pin directly tied to VOUT (load sense point) for accurate output voltage result.
  • Pins 6, 7, and 26 are not connected in the 25-A TPS548B22, while pins 6 and 7 connect to SW and pin 26 connects to PVIN in the 40-A TPS548D22.

Layout Example

TPS548B22 evm_topview_SLUSCE4.gif Figure 27. EVM Top View
TPS548B22 evm_inner_layer1_SLUSCE4.gif Figure 29. EVM Inner Layer 1
TPS548B22 evm_layer6_SLUSCE4.gif Figure 31. EVM Inner Layer 3
TPS548B22 evm_bottom_layer_SLUSCE4.gif Figure 33. EVM Bottom Layer
TPS548B22 evm_top_layer_SLUSCE4.gif Figure 28. EVM Top Layer
TPS548B22 evm_inner_layer2_SLUSCE4.gif Figure 30. EVM Inner Layer 2
TPS548B22 evm_layer4_SLUSCE4.gif Figure 32. EVM Inner Layer 4
TPS548B22 evm_bottom_symbols_SLUSCE4.gif Figure 34. EVM Bottom Symbols

Mounting and Thermal Profile Recommendation

Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the reflow process can affect electrical performance. Figure 35 shows the recommended reflow oven thermal profile. Proper post-assembly cleaning is also critical to device performance. See TI Application Report QFN/SON PCB Attachment for more information.

TPS548B22 mech_thermal_profile_slusc81.gif Figure 35. Recommended Reflow Oven Thermal Profile

Table 9. Recommended Thermal Profile Parameters

rRAMP(up) Average ramp-up rate, TS(max) to TP 3 °C/s
rRAMP(down) Average ramp-down rate, TP to TS(max) 6 °C/s
TS Pre-heat temperature 150 200 °C
tS Pre-heat time, TS(min) to TS(max) 60 180 s
TL Liquidus temperature 217 °C
TP Peak temperature 260 °C
tL Time maintained above liquidus temperature, TL 60 150 s
tP Time maintained within 5 °C of peak temperature, TP 20 40 s
t25P Total time from 25 °C to peak temperature, TP 480 s