SLVSGM2 March   2023 TPS548C26

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC and VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC_OK UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Fixed PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Set the Output Voltage
      4. 7.3.4  Differential Remote Sense and Feedback Divider
      5. 7.3.5  Start-up and Shutdown
      6. 7.3.6  Loop Compensation
      7. 7.3.7  Set Switching Frequency and Operation Mode
      8. 7.3.8  Switching Node (SW)
      9. 7.3.9  Overcurrent Limit and Low-side Current Sense
      10. 7.3.10 Negative Overcurrent Limit
      11. 7.3.11 Zero-Crossing Detection
      12. 7.3.12 Input Overvoltage Protection
      13. 7.3.13 Output Undervoltage and Overvoltage Protection
      14. 7.3.14 Overtemperature Protection
      15. 7.3.15 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 7.4.3 Powering the Device from a 12-V Bus
      4. 7.4.4 Powering the Device From a Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC and VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 PG Pullup Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS548C26 Evaluation Board
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Start-up and Shutdown

Start-up

The start-up sequence includes three sequential periods. During the first period, the device does initialization which includes building up internal LDOs and references, internal memory initialization, pin strap detection, and so forth. The initialization, which is not gated by EN pin voltage, starts as long as VCC pin voltage is above the VCC_OK UVLO rising threshold (3.15 V typical). The length of this period is about 300 μs for TPS548C26 device. The pin strap detection result is locked in after the initialization is finished and as long as VCC voltage stays above VCC_OK falling threshold. Changing the external resistor value does not affect the existing pin strap detection result unless the IC is power cycled.

After the EN pin voltage crosses above EN high threshold (typically 1.2 V) the device moves to the second period, power-on delay. The power-on delay is 0.5 ms to activate the control loop and the driver circuit.

The VOUT soft start is the third period. A soft-start ramp, which is an internal signal, starts right after the power-on delay. When starting up without pre-bias on the output, the internal reference ramps up from 0 V to 0.8 V, and the VOUT ramps up from 0 V to the setting value (by FB voltage divider). A proper soft-start time helps to avoid the inrush current by the output capacitor charging, and also minimize VOUT overshoot. The soft-start time can be selected among 4 options of 1 ms, 2 ms, 4 ms, and 8 ms by connecting a resistor from pin 29 SS to AGND. #GUID-77ADAFFF-9AC0-4F06-8DB0-9FD00911B7A3/TABLE_YWK_WX3_S5B lists the resistor values and the corresponding soft-start time. TI recommends ±1% tolerance resistors with a typical temperature coefficient of ±100 ppm/°C.

For the start-up with a pre-biased output the device limits the discharge current from the pre-biased output voltage by preventing the low-side FET from forcing the SW node low until after the first PWM pulse turns on the high-side FET. After the increasing reference voltage exceeds the feedback voltage which is divided down from the pre-biased output voltage, the SW pulses start. This enables a smooth startup with a pre-biased output.

After VOUT reaches the regulation value, a 1-ms PG delay starts. The converter then asserts PG pin when the 1-ms PG delay expires.

Table 7-1 SS Pin Strap for the Soft-start Time, Fault Response, and Internal Compensation
SS Pin to AGND Resistor (kΩ) Soft-start time (ms) Internal Compensation VOUT OV, UV Fault Response
0 1 Compensation1 Latch-off
1.50 2
2.49 4
3.48 8
4.53 1 Compensation2
5.76 2
7.32 4
8.87 8
10.5 1 Compensation1 Hiccup
12.1 2
14.0 4
16.2 8
18.7 1 Compensation2
21.5 2
24.9 4
28.7 8
Floating 4 Compensation1 Latch-off
Note: The pin strap detection happens at the first stage of power-up sequence. After the detection finishes, the detection results are latched in and do not change during the following operation. If a new selection is desired, toggling VCC (or AVIN) is required. Toggling the EN pin does not affect the pin strap detection results.

Shutdown

The TPS548C26 device features a simple shutdown sequence. Both high-side and low-side FET drivers are turned off immediately at the time when the EN pin is pulled low, and the output voltage discharge slew rate is controlled by the external load. The internal reference is discharged down to zero to get ready for the next soft start.