SNVSB02C March   2020  – July 2021 TPS54JA20

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO And Using External Bias On VCC Pin
      2. 7.3.2  Enable
      3. 7.3.3  Output Voltage Setting
        1. 7.3.3.1 Remote Sense
      4. 7.3.4  Internal Fixed Soft Start and External Adjustable Soft Start
      5. 7.3.5  External REFIN For Output Voltage Tracking
      6. 7.3.6  Frequency and Operation Mode Selection
      7. 7.3.7  D-CAP3 Control
      8. 7.3.8  Low-side FET Zero-Crossing
      9. 7.3.9  Current Sense and Positive Overcurrent Protection
      10. 7.3.10 Low-side FET Negative Current Limit
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Out-Of-Bounds (OOB) Operation
      14. 7.3.14 Output Voltage Discharge
      15. 7.3.15 UVLO Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Powering The Device From A 12-V Bus
      4. 7.4.4 Powering The Device From A 3.3-V Bus
      5. 7.4.5 Powering The Device From A Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setting Point
        2. 8.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 8.2.2.3  Choose the Inductor
        4. 8.2.2.4  Set the Current Limit (TRIP)
        5. 8.2.2.5  Choose the Output Capacitor
        6. 8.2.2.6  Choose the Input Capacitors (CIN)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance On TI EVM
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 External REFIN For Output Voltage Tracking

The TPS54JA20 provides an analog input pin (SS/REFIN) to accept an external reference (that is, a DC voltage source). The device always looks at the voltage on this SS/REFIN pin as the reference for the control loop. When an external voltage reference is applied between the SS/REFIN pin and VSNS– pin, it acts as the reference voltage, thus the FB voltage follows this external voltage reference exactly. The same ±0.6% SS/REFIN-to-FB accuracy from -40°C to 125°C applies here too.

In the middle of internal power-on delay, a detection circuit senses the voltage on the SS/REFIN pin to tell you whether an active DC voltage source is applied. Before the detection happens, the SS/REFIN pin tries to discharge any energy on the SS/REFIN capacitors through an internal 120-Ω resistor to AGND. This discharge lasts for 125 µs. Then, within a 32-µs window, the detection circuit compares the SS/REFIN pin voltage with an internal reference equal to 89% of VINTREF. This discharge operation ensures a SS capacitor with left-over energy will not be wrongly detected as a voltage reference. If the external voltage reference fails to supply sufficient current and hold voltage level higher than 89% of VINTREF, the SS/REFIN detection circuit will provide a wrong detection result.

If the detection result is that the SS/REFIN pin voltage falls below 89% of VINTREF which tells you no external reference is connected, the device first uses the internal fixed VINTREF as the reference for the PGOOD threshold, VOUT OVP, and VOUT UVP threshold. On this configuration, given the SS/REFIN pin sees a soft-start ramp on this pin, the slower ramp among the internal fixed soft start and the external soft start determines the start-up of FB. Once both the internal and external soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal goes high when FB reaches a threshold equal to VINTREF – 50 mV. The device waits for the PGOOD status transition from low to high, then starts using the SS/REFIN pin voltage instead of the internal VINTREF as the reference for PGOOD threshold, VOUT OVP, and VOUT UVP threshold.

If the detection result is that the SS/REFIN pin voltage holds higher than 89% of VINTREF which tells you an active DC voltage source is used as an external reference, the device always uses the SS/REFIN pin voltage, instead of the internal VINTREF, as the reference for PGOOD threshold, VOUT OVP, and VOUT UVP threshold. On this configuration, since the SS/REFIN pin sees a DC voltage and no soft-start ramp on this pin, the internal fixed soft start is used for start-up. Once the internal soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish because the soft-start ramp goes beyond VINTREF.

On this external REFIN configuration, applying a stabilized DC external reference to the SS/REFIN pin before EN high signal is recommended. During the internal power-on delay, the external reference should be capable to hold the SS/REFIN pin equal to or higher than 89% of VINTREF, so that the device can correctly detect the external reference and choose the right thresholds for Power Good, VOUT OVP, and VOUT UVP. After the Power Good status transits from low to high, the external reference can be set in a range of 0.5 V to 1.2 V. To overdrive the SS/REFIN pin during nominal operation, the external reference has to be able to sink more than 36-µA current if the external reference is lower than the internal VINTREF, or source more than 12-µA current if the external reference is higher than the internal VINTREF. When driving the SS/REFIN pin by an external reference through a resistor divider, the resistance of the divider should be low enough to provide the sinking or sourcing current capability.

The configuration of applying the EN high signal first, then applying an external ramp on the SS/REFIN pin as a tracking reference can be achieved, as long as design considerations for Power Good, VOUT OVP, and VOUT UVP have been taken. Please contact Texas Instruments for detailed information about this configuration.

If the external voltage source must transition up and down between any two voltage levels, the slew rate must be no more than 1 mV/μs.