SLVSH62 November   2023 TPS61033-Q1 , TPS610333-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Lockout
      2. 7.3.2  Enable and Soft Start
      3. 7.3.3  Setting the Output Voltage
      4. 7.3.4  Current Limit Operation
      5. 7.3.5  Pass-Through Operation
      6. 7.3.6  Power Good Indicator
      7. 7.3.7  Implement Output Discharge by PG function
      8. 7.3.8  Spread Spectrum Frequency Modulation
      9. 7.3.9  Overvoltage Protection
      10. 7.3.10 Output Short-to-Ground Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Mode
      2. 7.4.2 Power-Save Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Implement Output Discharge by PG function

The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage and to let the output voltage close to 0 V quickly when the device is being disabled. TPS61033-Q1 can implement output discharge function by PG function that requires a RDummy resistor connected between PG pin and Vout pin. PG is an open drain NMOS architecture with up to 50 mA current capability, the PG pin becomes logic high when the output voltage reaches the target value, so the dummy load resistor does not lead any power loss during normal operation. When the EN pin gets low, the TPS61033-Q1 is disabled and meanwhile the PG pin gets low with a typical 33μs glitch time (tglitch). With PG pin keep low, the RDummy works as a dummy load to discharge output voltage. Changing RDummy can adjust the output discharge rate.

GUID-F6ECCC49-249C-49E1-8517-9294211D92E9-low.svgFigure 7-1 Implement Output Discharge by PG function