SLVSC25B July   2013  – June 2017 TPS61197

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supply Voltage
      2. 7.3.2 Boost Controller
      3. 7.3.3 Switching Frequency
      4. 7.3.4 Enable and Undervoltage Lockout
      5. 7.3.5 Power-Up Sequencing and Soft Start-up
      6. 7.3.6 Current Regulation
      7. 7.3.7 PWM Dimming
      8. 7.3.8 Indication for Fault Conditions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Protections
        1. 7.4.1.1 Switch Current Limit Protection Using the ISNS Pin
        2. 7.4.1.2 LED Open Protection
        3. 7.4.1.3 Schottky Diode Open Protection
        4. 7.4.1.4 Schottky Diode Short Protection
        5. 7.4.1.5 IFB Overvoltage Protection
        6. 7.4.1.6 Output Overvoltage Protection Using the OVP Pin
        7. 7.4.1.7 IFB Short-to-Ground Protection
        8. 7.4.1.8 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Simple Boost Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Inductor Selection
          2. 8.2.1.2.2 Output Capacitor
          3. 8.2.1.2.3 Schottky Diode
          4. 8.2.1.2.4 Switch MOSFET and Gate Driver Resistor
          5. 8.2.1.2.5 Current Sense and Current Sense Filtering
          6. 8.2.1.2.6 Loop Consideration
        3. 8.2.1.3 Application Curves
      2. 8.2.2 PWM Dimming Controlled by Boost Converter
      3. 8.2.3 High Boost Ratio Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. The VDD capacitor, C3 (see Figure 18) is the filter and noise decoupling capacitor for the internal linear regulator powering the internal circuitries. It must be placed as close as possible between the VDD and PGND pin to prevent any noise insertion to internal circuitry. The switch node at the drain of Q1 carries high current with fast rising and falling edges. Therefore, the connection between this node to the inductor and the Schottky diode must be kept as short and wide as possible. The ground of output capacitor EC2 must be kept close to input power ground or through a large ground plane because of the large ripple current returning to the input ground. When laying out signal grounds, TI recommends using short traces separate from power ground traces and connecting them together at a single point. Resistors R3, R4, and R7 (see Figure 18) are setting resistors for switching frequency and output overvoltage protection. To avoid unexpected noise coupling into the pins and affecting the accuracy, these resistors must be close to the pins with short and wide traces to AGND pin.

10.2 Layout Example

TPS61197 layout_lvsc25.gif Figure 23. TPS61197 Layout