SLVS806D April   2009  – December 2015 TPS61240 , TPS61241

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
      1. 7.6.1 Table of Graphs
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Operation
      2. 9.3.2 Current Limit Operation
      3. 9.3.3 Undervoltage Lockout
      4. 9.3.4 Input Overvoltage Protection
      5. 9.3.5 Enable
      6. 9.3.6 Soft Start
      7. 9.3.7 Load Disconnect
      8. 9.3.8 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Save Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Programming the Output Voltage
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Checking Loop Stability
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Chip Scale Package Dimensions

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VI Input voltage on VIN, L, EN –0.3 7 V
Voltage on VOUT –2.0 7 V
Voltage on FB –2.0 14 V
Peak output current Internally limited A
TJ Maximum operating junction temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge(2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
Machine model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN Input voltage range 2.3 5.5 V
L Inductance 0.4 1 1.5 µH
CO Output capacitance TPS61240
TPS61241		 1 20 µF
TPS61242 0.8 10 µF
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125

7.4 Thermal Information

THERMAL METRIC(1) TPS6124x UNIT
YFF DRV
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 132.7 104.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1.2 97.1
RθJB Junction-to-board thermal resistance 22.4 74.0
ψJT Junction-to-top characterization parameter 5.2 4.5
ψJB Junction-to-board characterization parameter 22.4 74.4
RθJC(bot) Junction-to-case (bottom) thermal resistance — 48.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6V. External components CIN = 2.2μF, COUT = 4.7μF 0603, L = 1μH, refer to Parameter Measurement Information section.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC-DC STAGE
VIN Input voltage range 2.3 5.5 V
VOUT Fixed output voltage range 2.3 V ≤ VIN ≤ 5.5 V, 0 mA ≤ IOUT ≤ 200 mA 4.9 5.0 5.1 V
VO_Ripple Ripple voltage, PWM mode ILOAD = 150 mA 20 mVpp
ISW Output current VIN 2.3 V to 5.5 V 200 mA
Switch valley current limit VOUT = VGS = 5.0 V (TPS61240) 500 600 mA
VOUT = VGS = 5.0 V (TPS61241, TPS61242) 600 700
Short circuit current VOUT = VGS = 5.0 V 200 350 mApk
High side MOSFET on-resistance(1) VIN = VGS = 5.0 V, TA = 25°C(1) 290 mΩ
Low Side MOSFET on-resistance(1) VIN = VGS = 5.0 V, TA = 25°C (1) 250 mΩ
Operating quiescent current IOUT = 0 mA, Power save mode 30 40 μA
Shutdown current EN = GND 1.5 μA
Reverse leakage current VOUT EN = 0, VOUT = 5 V 2.5 μA
Leakage current from battery to VOUT EN = GND 2.5 μA
Line transient response VIN 600 mVp-p AC square wave, 200 Hz,
12.5% DC at 50/200 mA load		 ±25 ±50 mVpk
Load transient response 0–50 mA, 50–0 mA VIN = 3.6V TRise = TFall = 0.1 μs 50 mVpk
50–200 mA, 200–50 mA, VIN = 3.6 V, TRise = TFall = 0.1 μs 150
IIN Input bias current, EN EN = GND or VIN 0.01 1.0 μA
VUVLO Undervoltage lockout threshold Falling 2.0 2.1 V
Rising 2.1 2.2 V
CONTROL STAGE
VIH High level input voltage threshold, EN 2.3 V ≤ VIN ≤ 5.5 V 1.0 V
VIL Low level input voltage threshold, EN 2.3 V ≤ VIN ≤ 5.5 V 0.4 V
OVC Input overvoltage threshold Falling 5.9 V
Rising 6.0
tStart Start-up time Time from active EN to start switching, no-load until VOUT is stable 5 V 300 μs
DC-DC STAGE
ƒ See Figure 7 (Frequency Dependancy vs IOUT) 3.5 MHz
TSD Thermal shutdown Increasing junction temperature 140 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
(1) DRV package has an increased RDSon of about 40mΩ due to bond wire resistance.

7.6 Typical Characteristics

7.6.1 Table of Graphs

Figure
Maximum Output Current vs Input Voltage Figure 1
Efficiency vs Output Current, Vout = 5V, Vin = [2.3 V; 3.0 V; 3.6 V; 4.2 V] Figure 2
vs Input Voltage, Vout = 5 V, Iout = [100 µA; 1 mA; 10 mA; 100 mA; 200 mA] Figure 3
Input Current at No Output Load, Device Disabled Figure 4
Output Voltage vs Output Current, Vout = 5 V, Vin = [2.3 V; 3.0 V; 3.6 V; 4.2 V] Figure 5
vs Input Voltage Figure 6
Frequency vs Output Load, Vout = 5 V, Vin = [3.0 V; 4.0 V; 5.0 V] Figure 7
TPS61240 TPS61241 io_vi_lvs806.gif Figure 1. Maximum Output Current vs Input Voltage
TPS61240 TPS61241 eff_via_lvs806.gif Figure 3. Efficiency vs Input Voltage
TPS61240 TPS61241 voa_io_lvs806.gif Figure 5. Output Voltage vs Output Current
TPS61240 TPS61241 freqa_io_lvs806.gif Figure 7. Frequency vs Output Load
TPS61240 TPS61241 effa_io_lvs806.gif Figure 2. Efficiency vs Output Current
TPS61240 TPS61241 iiq_vi_lvs806.gif Figure 4. Input at No Output Load
TPS61240 TPS61241 vo_vi_lvs806.gif Figure 6. Output Voltage vs Input Voltage