SLVSDZ7A September   2017  – December 2017 TPS62097-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      1.8-V Output, Typical Application
      2.      1.8-V Output, Efficiency, MODE = Open
  4. 4 Revision History
  5. 5 Terminal Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommend Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 100% Duty Cycle Mode
      2. 7.3.2 Switch Current Limit and Hiccup Short Circuit Protection
      3. 7.3.3 Under Voltage Lockout (UVLO)
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Function Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Power Save Mode and Forced PWM Mode (MODE)
      3. 7.4.3 Soft Startup (SS/TR)
      4. 7.4.4 Voltage Tracking (SS/TR)
      5. 7.4.5 Power Good (PG)
  8. 8 Application Information
    1. 8.1 Application Information
    2. 8.2 1.8-V Output Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Output Filter Design
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Capacitor Selection
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Information
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

  • TI recommends to place all components as close as possible to the IC. Specially, the input capacitor placement must be closest to the PVIN and PGND pins of the device.
  • The low side of the input and output capacitors must be connected directly to the PGND pin to avoid a ground potential shift.
  • Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
  • The sense trace connected to VOS pin is a signal trace. Special care should be taken to avoid noise being induced. Keep the trace away from SW nodes.
  • Refer to Figure 25 for an example of component placement, routing and thermal design.