SLVSDZ7A September   2017  – December 2017 TPS62097-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      1.8-V Output, Typical Application
      2.      1.8-V Output, Efficiency, MODE = Open
  4. 4 Revision History
  5. 5 Terminal Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommend Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 100% Duty Cycle Mode
      2. 7.3.2 Switch Current Limit and Hiccup Short Circuit Protection
      3. 7.3.3 Under Voltage Lockout (UVLO)
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Function Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Power Save Mode and Forced PWM Mode (MODE)
      3. 7.4.3 Soft Startup (SS/TR)
      4. 7.4.4 Voltage Tracking (SS/TR)
      5. 7.4.5 Power Good (PG)
  8. 8 Application Information
    1. 8.1 Application Information
    2. 8.2 1.8-V Output Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Output Filter Design
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Capacitor Selection
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Information
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.5 Power Good (PG)

The TPS62097-Q1 has a power good output. The PG pin goes high impedance once the output voltage is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. The PG pin is an open drain output and is specified to sink up to 1mA. The power good output requires a pull-up resistor connected to any voltage rail less than 6V. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin floating when not used. Table 2 shows the PG pin logic.

Table 2. PG Pin Logic

Device Conditions Logic Status
High ZLow
Enable EN = High, VFB ≥ VPG √
EN = Low, VFB ≤ VPG √
Shutdown EN = Low √
Thermal Shutdown TJ > TJSD √
UVLO 0.7 V < VIN < VUVLO √
Power Supply Removal VIN ≤ 0.7 V √