SLVSAQ5E March 2012 – May 2017 TPS62125
The TPS62125 high-efficiency synchronous switch mode buck converter includes TI's DCS-Control (Direct Control with Seamless Transition into Power-Save Mode), an advanced regulation topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of DCS-Control are excellent AC load regulation and transient response, low-output ripple voltage and a seamless transition between PFM and PWM mode operation.
DCS-Control includes an AC loop which senses the output voltage (VOS pin) and directly feeds the information to a fast comparator stage. This comparator sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. In order to achieve accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The DCS-Control topology supports pulse width modulation (PWM) mode for medium and high load conditions and a power-save mode at light loads. During PWM mode, it operates in continuous conduction. The switch frequency is up to 1 MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter seamless enters power-save mode to maintain high efficiency down to very light loads. In power-save mode the switching frequency varies linearly with the load current. Because DCS-Control supports both operation modes within one single building block, the transition from PWM to power-save mode is seamless without effects on the output voltage. The TPS62125 offers both excellent DC voltage and superior load transient regulation, combined with very low-output voltage ripple, minimizing interference with RF circuits.
At high load currents the converter operates in quasi fixed frequency PWM mode operation and at light loads in pulse frequency modulation (PFM) mode to maintain highest efficiency over the full load current range. In PFM mode, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to achieve a quiescent current of typically 13 µA. During this time, the load current is supported by the output capacitor. The duration of the sleep period depends on the load current and the inductor peak current.
In addition to the EN comparator, the device includes an under-voltage lockout circuit which prevents the device from misoperation at low input voltages. Both circuits are fed to an AND gate and prevents the converter from turning on the high-side MOSFET switch or low-side MOSFET under undefined conditions. The UVLO threshold is set to 2.9 V typical for rising VIN and 2.8 V typical for falling VIN. The hysteresis between rising and falling UVLO threshold ensures proper start-up. Fully functional operation is permitted for an input voltage down to the falling UVLO threshold level. The converter starts operation again once the input voltage trips the rising UVLO threshold level and the voltage at the EN pin trips VTH_EN_ON.
The EN pin is connected to an on/shutdown detector (ON/SD) and an input of the enable comparator. With a voltage level of 0.4 V or less at the EN pin, the ON/SD detector turns the device into Shutdown mode and the quiescent current is reduced to typically 350 nA. In this mode the EN comparator as well the entire internal-control circuitry are switched off. A voltage level of typical 900 mV (rising) at the EN pin triggers the on/shutdown detector and activates the internal reference VREF (typical 1.2 V), the EN comparator and the UVLO comparator. In applications with slow rising voltage levels at the EN pin, the quiescent current profile before this trip point needs to be considered, see Figure 3. Once the ON/SD detector has tripped, the quiescent current consumption of the device is typical 6 µA. The TPS62125 starts regulation once the voltage at the EN pin trips the threshold VEN_TH ON (typical 1.2 V) and the input voltage is above the UVLO threshold. It enters softstart and ramps up the output voltage. For proper operation, the EN pin must be terminated and must not be left floating. The quiescent current consumption of the TPS62125 is typical 13 µA under no load condition (not switching). See Figure 1. The DC/DC regulator stops operation once the voltage on the EN pin falls below the threshold VEN_TH OFF (typical 1.15 V) or the input voltage falls below UVLO threshold. The enable comparator features a built in hysteresis of typical 50 mV. This hysteresis can be increased with an external resistor connected to pin EN_hys.
The power good output (PG pin) is an open drain output. The circuit is active once the device is enabled. It is driven by an internal comparator connected to the FB pin voltage and an internal reference. The PG output provides a high level (open drain high impedance) once the feedback voltage exceeds typical 95% of its nominal value. The PG output is driven to low level once the FB pin voltage falls below typical 90% of its nominal value VREF_FB. The PG output goes high (high impedance) with a delay of typically 2 µs. A pull up resistor is needed to generate a high level. The PG pin can be connected via a pull up resistors to a voltage up to 10 V. This pin can also be used to discharge the output capacitor. See section Application Information for more details.
The PG output is pulled low if the voltage on the EN pin falls below the threshold VEN_TH OFF or the input voltage is below the undervoltage lockout threshold UVLO.
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis.
The TPS62125 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal switching frequency of about 1 MHz. The frequency variation in PWM mode is controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device enters power-save mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the inductor's ripple current.
With decreasing load current, the TPS62125 transitions seamlessly from PWM mode to power-save mode once the inductor current becomes discontinuous. This ensures a high efficiency at light loads. In power-save mode the converter operates in pulse frequency modulation (PFM) mode and the switching frequency decreases linearly with the load current. DCS-Control features a small and predictable output voltage ripple in power-save mode. The transition between PWM mode and power-save mode occurs seamlessly in both directions.
The minimum ON-time TONmin for a single pulse can be estimated by:
Therefore the peak inductor current in PFM mode is approximately:
The transition from PFM mode to PWM mode operation and back occurs at a load current of approximately 0.5 x ILPFMpeak.
The maximum switching frequency can be estimated by:
The device increases the ON-time of the high-side MOSFET switch as the input voltage comes close to the output voltage in order to keep the output voltage in regulation. This reduces the switching frequency.
With further decreasing input voltage VIN, the high-side MOSFET switch is turned on completely. In this case, the converter provides a low input-to-output voltage difference. This is particularly useful in applications with a widely variable supply voltage to achieve longest operation time by taking full advantage of the whole supply voltage span.
The minimum input voltage to maintain output voltage regulation depends on the load current and output voltage, and can be calculated as:
The TPS62125 has an internal soft-start circuit which controls the ramp up of the output voltage and limits the inrush current during start-up. This limits input voltage drop.
The soft-start system generates a monotonic ramp up of the output voltage and reaches an output voltage of 1.8 V typical within 240 µs after the EN pin was pulled high. For higher output voltages, the ramp up time of the output voltage can be estimated with a ramp up slew rate of about 12 mV/us. TPS62125 is able to start into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value. In case the output voltage is higher than the nominal value, the device starts switching once the output has been discharged by an external load or leakage current to its nominal output voltage value.
During start-up the device can provide an output current of half of the high-side MOSFET switch current limit ILIMF. Large output capacitors and high load currents may exceed the current capability of the device during start-up. In this case the start-up ramp of the output voltage will be slower.
The TPS62125 integrates a high-side MOSFET switch current limit, ILIMF, to protect the device against a short circuit. The current in the high-side MOSFET switch is monitored by a current limit comparator and once the current reaches the limit of ILIMF , the high-side MOSFET switch is turned off and the low-side MOSFET switch is turned on to ramp down the inductor current. The high-side MOSFET switch is turned on again once the zero current comparator trips and the inductor current has become zero. In this case, the output current is limited to half of the high-side MOSFET switch current limit, 0.5 x ILIMF, typ. 300mA.