SLVSAQ5E March   2012  – May 2017 TPS62125


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Enable Comparator (EN / EN_hys)
      3. 7.3.3 Power Good Output and Output Discharge (PG)
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation (PWM) Operation
      2. 7.4.2 Power-Save Mode
      3. 7.4.3 100% Duty Cycle Low Dropout Operation
      4. 7.4.4 Soft-Start
      5. 7.4.5 Short-Circuit Protection
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Output Voltage Setting
        2. Enable Threshold and Hysteresis Setting
        3. Power Good (PG) Pullup and Output Discharge Resistor
        4. Output Filter Design (Inductor and Output Capacitor)
        5. Inductor Selection
        6. Output Capacitor Selection
        7. Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 TPS62125 5-V Output Voltage Configuration
      2. 8.3.2 TPS62125 5-V VOUT
      3. 8.3.3 TPS62125 Operation From a Storage Capacitor Charged From a 0.5 mA Current Source
      4. 8.3.4 5 V to -5 V Inverter Configuration
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Take care in the board layout to get the specified performance. If the layout is not carefully done, the regulator could show frequency variations, poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low-inductance, low-impedance ground path. Therefore, use wide and short traces for the paths conducting AC current of the DC/DC converter. The area of the AC current loop (input capacitor – TPS62125 – inductor – output capacitor) should be routed as small as possible to avoid magnetic field radiation. Therefore the input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Use a common power GND node and a different node for the signal GND to minimize the effects of ground noise. Keep the common path to the GND pin, which returns both the small signal components and the high current of the output capacitors as short as possible to avoid ground noise. A well proven practice is to merge small signal GND and power GND path at the exposed thermal pad. The FB divider network and the FB line should be routed away from the inductor and the SW node to avoid noise coupling. The VOS line should be connected as short as possible to the output, ideally to the VOUT terminal of the inductor. Keep the area of the loop VOS node – inductor – SW node small. The exposed thermal pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation.

Layout Example

TPS62125 Layout_ds.gif Figure 61. EVM Board Layout