SLVSAI5B September   2010  – June 2016 TPS62290-Q1 , TPS62293-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
        1. 8.3.1.1 Dynamic Voltage Positioning
        2. 8.3.1.2 100% Duty Cycle Low Dropout Operation
        3. 8.3.1.3 Undervoltage Lockout
      2. 8.3.2 Enable
      3. 8.3.3 Soft Start
      4. 8.3.4 Short-Circuit Protection
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS62290DRV Adjustable 1.8 V
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Voltage Setting
          2. 9.2.1.2.2 Output Filter Design (Inductor and Output Capacitor)
            1. 9.2.1.2.2.1 Inductor Selection
            2. 9.2.1.2.2.2 Output Capacitor Selection
            3. 9.2.1.2.2.3 Input Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 TPS62290DRV Adjustable 3.3 V
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 TPS62293DRV Fixed 1.8 V
        1. 9.2.3.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage(2) –0.3 7 V
Voltage at EN, MODE –0.3 VIN +0.3, ≤ 7
Voltage on SW(3) –0.3 7
Peak output current Internally limited A
TJ Maximum operating junction temperature –40 125 °C
Tstg Storage temperature –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) I = Input, O = Output, GND = Ground, PWR = Power

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN Supply voltage 2.3 6 V
Output voltage for adjustable voltage 0.6 VIN V
TA Operating ambient temperature TPS62290IDRVRQ1 –40 85 °C
TPS6229XTDRVRQ1 –40 105
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS6229x-Q1 UNIT
DRV (SON)
6 PINS
RθJA Junction-to-ambient thermal resistance 67.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 88.5 °C/W
RθJB Junction-to-board thermal resistance 37.2 °C/W
ψJT Junction-to-top characterization parameter 2 °C/W
ψJB Junction-to-board characterization parameter 37.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6 V. External components CIN = 4.7 µF 0603, COUT = 10 µF 0603, L = 2.2 µH, see Parameter Measurement Information.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VI Input voltage 2.3 6 V
IO Output current(4) VIN 2.7 V to 6 V 1000 mA
VIN 2.5 V to 2.7 V 600
VIN 2.3 V to 2.5 V 300
IQ Operating quiescent current IO = 0 mA, PFM mode enabled
(MODE = GND) device not switching, See (1) 		15 µA
IO = 0 mA, switching with no load,
(MODE = VIN)
PWM operation, VO = 1.8 V, VIN = 3V		 3.8 mA
ISD Shutdown current EN = GND TA = 25°C 0.1 1 µA
TA = 105°C 2.5
UVLO Undervoltage lockout threshold Falling 1.85 V
Rising 1.95
ENABLE, MODE
VIH High level input voltage, EN, MODE 2.3 V ≤ VIN ≤ 6 V 1 VIN V
VIL Low level input voltage, EN, MODE 2.3 V ≤ VIN ≤ 6 V 0 0.4 V
II Input bias current, EN, MODE EN, MODE = GND or VIN 0.01 1 µA
POWER SWITCH
RDS(on) High-side MOSFET ON-resistance VIN = VGS = 3.6 V, TA = 25°C 240 480 mΩ
Low-side MOSFET ON-resistance 185 380
ILIMF Forward current limit MOSFET high-side and low-side VIN = VGS = 3.6 V, TA = 25°C 1.19 1.4 1.78 A
TSD Thermal shutdown Increasing junction temperature 140 °C
Thermal shutdown hysteresis Decreasing junction temperature 20
OSCILLATOR
fSW Oscillator frequency 2.3 V ≤ VIN  ≤ 6 V 2 2.25 2.5 MHz
OUTPUT
VO Adjustable output voltage range 0.6 VI V
Vref Reference voltage 600 mV
VFB(PWM) Feedback voltage MODE = VIN, PWM operation,
2.3 V ≤ VIN  ≤ 6 V, See (2) 		–1.5% 0% 1.5%
VFB(PFM) Feedback voltage PFM mode MODE = GND, device in PFM mode, +1% voltage positioning active, See (1) 1%
Load regulation –0.5 %/A
tStart Up Start-up time Time from active EN to reach 95% of VO 500 µs
tRamp VO ramp-up time Time to ramp from 5% to 95% of VO 250 µs
Ilkg Leakage current into SW pin VI = 3.6 V, VI = VO = VSW, EN = GND,
See (3) 		0.1 1 µA
(1) In PFM mode, the internal reference voltage is set to 1.01 × Vref (typical). See Parameter Measurement Information.
(2) For VIN = VO + 1 V
(3) In fixed output voltage versions, the internal resistor divider network is disconnected from FB pin.
(4) Not production tested.

6.6 Typical Characteristics

Table 1. Table of Graphs

FIGURE NO.
Shutdown Current into VIN vs Input Voltage, (TA = 85°C, TA = 25°C, TA = –40°C) Figure 1
Quiescent Current vs Input Voltage, (TA = 85°C, TA = 25°C, TA = –40°C) Figure 2
Static Drain-Source ON-State Resistance vs Input Voltage, (TA = 85°C, TA = 25°C, TA = –40°C) Figure 3
Figure 4
TPS62290-Q1 TPS62293-Q1 isd_v_vin_lvs762.gif
Figure 1. Shutdown Current into VIN vs Input Voltage
TPS62290-Q1 TPS62293-Q1 rds_hs_vin_lvs762.gif
Figure 3. Static Drain-Source ON-State Resistance vs Input Voltage
TPS62290-Q1 TPS62293-Q1 iq_v_vin_lvs762.gif
Figure 2. Quiescent Current vs Input Voltage
TPS62290-Q1 TPS62293-Q1 rds_ls_vin_lvs762.gif
Figure 4. Static Drain-Source ON-State Resistance vs Input Voltage