The TPS6240x family of devices are synchronous dual step-down DC-DC converters. The devices provide two independent output voltage rails. The following information gives guidance on choosing external components to complete the application design.
The step-down converter design can be adapted to different output voltage and load current needs by choosing external components appropriate. The following design procedure is adequate for whole VIN, VOUT and load current range of TPS6240x.
The output voltage can be calculated to:
To keep the operating current to a minimum, it is recommended to select R12 within a range of 180kΩ to 360kΩ. The sum of R12 and R11 should not exceed ~1MΩ. For higher output voltages than 3.3V, it is recommended to choose lower values than 180kΩ for R12. Route the DEF_1 line away from noise sources, such as the inductor or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. A feed-forward capacitor is not necessary.
The output voltage VOUT1 is selected with DEF_1 pin.
Pin DEF_1 = low:
TPS62401, TPS62403 = 1.575V
Pin DEF_1 = high:
TS62401, TPS62403 = 1.1V
T62402: = 1.8V
T62404: = 1.9V
The output voltage of converter 2 can be set by an external resistor network. For converter 2 the same recommendations apply as for converter1. In addition to that, a 33pF feed-forward Capacitor Cff2 for good load transient response should be used. The output voltage can be calculated to:
ADJ2 pin must be directly connected with VOUT2
TPS62401, VOUT2 default = 1.8V
TPS62403, VOUT2 default = 2.8V
TPS62402, TPS62404, VOUT2 default = 3.3V
The converters are designed to operate with a minimum inductance of 1.75μH and minimum capacitance of 6μF. The device is optimized to operate with inductors of 2.2μH to 4.7μH and output capacitors of 10μF to 22μF.
The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductor will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is recommended because during heavy load transient the inductor current rises above the calculated value.
f = Switching Frequency (2.25MHz typical)
L = Inductor Value
ΔIL = Peak-to-Peak inductor ripple current
ILmax = Maximum Inductor current
The highest inductor current occurs at maximum Vin.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. Take into consideration that the core material from inductor to inductor differs and this difference has an impact on the efficiency.
Refer to Table 7 and the typical application circuit examples for possible inductors.
|DIMENSIONS [mm3]||INDUCTOR TYPE||SUPPLIER|
The advanced fast response voltage mode control scheme of the converters allows the use of tiny ceramic capacitors with a typical value of 10μF to 22μF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors with low ESR values results in lowest output voltage ripple, and are therefore recommended. The output capacitor requires either X7R or X5R dielectric. Y5V and Z5U dielectric capacitors are not recommended due to their wide variation in capacitance.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. The RMS ripple current is calculated as:
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR, plus the voltage ripple caused by charging and discharging the output capacitor:
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. Higher output capacitors like 22μF values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM Mode.
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interference with other circuits in the system. An input capacitor of 10μF is sufficient.
VIN = 3.6 V, and TA = 25 °C, unless otherwise noted.
The TPS6240x is able to be set for different output voltages. Some examples are shown below.
The TPS6240x step-down converter is set to different output voltages.
Control the output voltage of the converter 1 through DEF_1 pin by an external processor.
Connect the DEF_1 pin to the VCore_Sel pin of an external processor, as shown in Figure 46. The processor determines the logic status of the DEF_1 pin which sets the output voltage of the converter 1.