SLVS681F June   2006  – August 2014 TPS62400 , TPS62401 , TPS62402 , TPS62403 , TPS62404


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Converter 1
      2. 8.3.2 Converter 2
      3. 8.3.3 DEF_1 Pin Function
      4. 8.3.4 Mode Selection
      5. 8.3.5 Enable
      6. 8.3.6 Soft Start
      7. 8.3.7 Short-Circuit Protection
      8. 8.3.8 Under-Voltage Lockout
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Save Mode
      2. 8.4.2 Dynamic Voltage Positioning
      3. 8.4.3 100% Duty Cycle Low Dropout Operation
      4. 8.4.4 180° Out-Of-Phase Operation
    5. 8.5 Programming
      1. 8.5.1 EasyScale: One-Pin Serial Interface for Dynamic Output Voltage Adjustment
        1. General
        2. Protocol
        3. Addressable Registers
          1. Bit Decoding
          2. Acknowledge
          3. MODE Selection
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS6240x, Dual Outputs Step Down Converter
        1. Design Requirements
        2. Detailed Design Procedure
          1. Converter1 Adjustable Default Output Voltage Setting: TPS62400
          2. Converter1 Fixed Default Output Voltage Setting (TPS62401, TPS62402, TPS62403, TPS62404).
          3. Converter 2 Adjustable Default Output Voltage Setting TPS62400:
          4. Converter 2 Fixed Default Output Voltage Setting
          5. Output Filter Design (Inductor and Output Capacitor)
            1. Inductor Selection
            2. Output Capacitor Selection
            3. Input Capacitor Selection
        3. Application Curves
      2. 9.2.2 Various Output Voltages
        1. Design Requirements
        2. Detailed Design Procedure
      3. 9.2.3 Dynamic Voltage Scaling on Converter 1 by DEF_1 Pin
        1. Design Requirements
        2. Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low-inductance, impedance ground path. Therefore, use wide and short traces for the main current paths as indicated in bold in Figure 48.

The input capacitor should be placed as close as possible to the IC pins VIN and GND, the inductor and output capacitor as close as possible to the pins SW1 and GND.

Connect the GND Pin of the device to the PowerPAD of the PCB and use this Pad as a star point. For each converter use a common Power GND node and a different node for the signal GND to minimize the effects of ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the common path to the GND PIN, which returns the small signal components and the high current of the output capacitors, as short as possible to avoid ground noise. The output voltage sense lines (FB 1, DEF_1, ADJ2) should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW1 and SW2 lines). If the EasyScale™ interface is operated with high transmission rates, the MODE/DATA trace must be routed away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling.

11.2 Layout Example

layout_lvs681.gifFigure 48. Layout Diagram
pcb_lvs681.gifFigure 49. PCB Layout