SLVS681F June   2006  – August 2014 TPS62400 , TPS62401 , TPS62402 , TPS62403 , TPS62404

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Converter 1
      2. 8.3.2 Converter 2
      3. 8.3.3 DEF_1 Pin Function
      4. 8.3.4 Mode Selection
      5. 8.3.5 Enable
      6. 8.3.6 Soft Start
      7. 8.3.7 Short-Circuit Protection
      8. 8.3.8 Under-Voltage Lockout
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Save Mode
      2. 8.4.2 Dynamic Voltage Positioning
      3. 8.4.3 100% Duty Cycle Low Dropout Operation
      4. 8.4.4 180° Out-Of-Phase Operation
    5. 8.5 Programming
      1. 8.5.1 EasyScale: One-Pin Serial Interface for Dynamic Output Voltage Adjustment
        1. 8.5.1.1 General
        2. 8.5.1.2 Protocol
        3. 8.5.1.3 Addressable Registers
          1. 8.5.1.3.1 Bit Decoding
          2. 8.5.1.3.2 Acknowledge
          3. 8.5.1.3.3 MODE Selection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS6240x, Dual Outputs Step Down Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Converter1 Adjustable Default Output Voltage Setting: TPS62400
          2. 9.2.1.2.2 Converter1 Fixed Default Output Voltage Setting (TPS62401, TPS62402, TPS62403, TPS62404).
          3. 9.2.1.2.3 Converter 2 Adjustable Default Output Voltage Setting TPS62400:
          4. 9.2.1.2.4 Converter 2 Fixed Default Output Voltage Setting
          5. 9.2.1.2.5 Output Filter Design (Inductor and Output Capacitor)
            1. 9.2.1.2.5.1 Inductor Selection
            2. 9.2.1.2.5.2 Output Capacitor Selection
            3. 9.2.1.2.5.3 Input Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Various Output Voltages
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Dynamic Voltage Scaling on Converter 1 by DEF_1 Pin
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

9.1 Application Information

The TPS6240x family of devices are synchronous dual step-down DC-DC converters. The devices provide two independent output voltage rails. The following information gives guidance on choosing external components to complete the application design.

9.2 Typical Applications

9.2.1 TPS6240x, Dual Outputs Step Down Converter

typ_app_cir_lvs681.gifFigure 14. Typical Application Circuit 1.5V/2.85V Adjustable Outputs, Low PFM Voltage Ripple Optimized
typ_app_cir2_lvs681.gifFigure 15. Typical Application Circuit 1.5V/2.85V Adjustable Outputs

9.2.1.1 Design Requirements

The step-down converter design can be adapted to different output voltage and load current needs by choosing external components appropriate. The following design procedure is adequate for whole VIN, VOUT and load current range of TPS6240x.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Converter1 Adjustable Default Output Voltage Setting: TPS62400

The output voltage can be calculated to:

Equation 4. q4_vout_lvs681.gif

To keep the operating current to a minimum, it is recommended to select R12 within a range of 180kΩ to 360kΩ. The sum of R12 and R11 should not exceed ~1MΩ. For higher output voltages than 3.3V, it is recommended to choose lower values than 180kΩ for R12. Route the DEF_1 line away from noise sources, such as the inductor or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. A feed-forward capacitor is not necessary.

9.2.1.2.2 Converter1 Fixed Default Output Voltage Setting (TPS62401, TPS62402, TPS62403, TPS62404).

The output voltage VOUT1 is selected with DEF_1 pin.

Pin DEF_1 = low:

TPS62401, TPS62403 = 1.575V

TPS62402, TPS62404 = 1.2V

Pin DEF_1 = high:

TS62401, TPS62403 = 1.1V

T62402: = 1.8V

T62404: = 1.9V

9.2.1.2.3 Converter 2 Adjustable Default Output Voltage Setting TPS62400:

The output voltage of converter 2 can be set by an external resistor network. For converter 2 the same recommendations apply as for converter1. In addition to that, a 33pF feed-forward Capacitor Cff2 for good load transient response should be used. The output voltage can be calculated to:

Equation 5. q5_vout1_lvs681.gif

9.2.1.2.4 Converter 2 Fixed Default Output Voltage Setting

ADJ2 pin must be directly connected with VOUT2

TPS62401, VOUT2 default = 1.8V

TPS62403, VOUT2 default = 2.8V

TPS62402, TPS62404, VOUT2 default = 3.3V

9.2.1.2.5 Output Filter Design (Inductor and Output Capacitor)

The converters are designed to operate with a minimum inductance of 1.75μH and minimum capacitance of 6μF. The device is optimized to operate with inductors of 2.2μH to 4.7μH and output capacitors of 10μF to 22μF.

9.2.1.2.5.1 Inductor Selection

The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductor will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency.

Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is recommended because during heavy load transient the inductor current rises above the calculated value.

Equation 6. q6_deltai_lvs681.gif
Equation 7. q7_ilmax_lvs681.gif

with:

f = Switching Frequency (2.25MHz typical)

L = Inductor Value

ΔIL = Peak-to-Peak inductor ripple current

ILmax = Maximum Inductor current

The highest inductor current occurs at maximum Vin.

Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. Take into consideration that the core material from inductor to inductor differs and this difference has an impact on the efficiency.

Refer to Table 7 and the typical application circuit examples for possible inductors.

Table 7. List of Inductors

DIMENSIONS [mm3] INDUCTOR TYPE SUPPLIER
3.2×2.6×1.0 MIPW3226 FDK
3×3×0.9 LPS3010 Coilcraft
2.8×2.6×1.0 VLF3010 TDK
2.8x2.6×1.4 VLF3014 TDK
3×3×1.4 LPS3015 Coilcraft
3.9×3.9×1.7 LPS4018 Coilcraft

9.2.1.2.5.2 Output Capacitor Selection

The advanced fast response voltage mode control scheme of the converters allows the use of tiny ceramic capacitors with a typical value of 10μF to 22μF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors with low ESR values results in lowest output voltage ripple, and are therefore recommended. The output capacitor requires either X7R or X5R dielectric. Y5V and Z5U dielectric capacitors are not recommended due to their wide variation in capacitance.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. The RMS ripple current is calculated as:

Equation 8. q8_irmscout_lvs681.gif

At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR, plus the voltage ripple caused by charging and discharging the output capacitor:

Equation 9. q9_deltav_lvs681.gif

Where the highest output voltage ripple occurs at the highest input voltage Vin.

At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. Higher output capacitors like 22μF values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM Mode.

9.2.1.2.5.3 Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interference with other circuits in the system. An input capacitor of 10μF is sufficient.

9.2.1.3 Application Curves

VIN = 3.6 V, and TA = 25 °C, unless otherwise noted.

eff_io_11_lvs681.gif
A.
Figure 16. Efficiency TPS62401 VOUT1 = 1.1V
eff_io_18_lvs681.gif
A.
Figure 18. Efficiency VOUT 2 = 1.8V
eff37_io_lvs681.gif
A.
Figure 20. Efficiency TPS62402 VOUT1/VOUT2
eff_19v_404_lvs681.gif
A.
Figure 22. Efficiency TPS62404 VOUT1 = 1.9V,
DEF_1 = HIGH
eff_vi_33_lvs681.gif
A.
Figure 24. EFFICIENCY vs VIN
vo_io_33_lvs681.gif
A.
Figure 26. DC Output Accuracy VOUT2 = 3.3V
dc_out2_lvs681.gif
A.
Figure 28. DC Output Accuracy VOUT1 = 1.575V,
L = 2.2μH, COUT = 22μF
ll_vo_lvs681.gif
Figure 30. Light Load Output Voltage Ripple In Power Save Mode
vo_pwm_lvs681.gif
Figure 32. Output Voltage Ripple In PWM Mode
ld_trns_lvs681.gif
Figure 34. Load Transient Response PFM/PWM
line_trn_lvs681.gif
Figure 36. Line Transient Response
typ_opr_lvs681.gif
Figure 38. Typical Operation VIN = 3.6V,
VOUT1 = 1.575V, VOUT2 = 1.8V
typ_opr3_lvs681.gif
Figure 40. Typical Operation VIN = 3.6V,
VOUT1 = 1.2V, VOUT2 = 1.2V
eff_io_15_lvs681.gif
A.
Figure 17. Efficiency TPS62401 VOUT1 = 1.575V
eff_io_33_lvs681.gif
A.
Figure 19. Efficiency TPS62400 VOUT 2 = 3.3V
eff3_io_lvs681.gif
A.
Figure 21. Efficiency TPS62403 VOUT1/VOUT2
eff_vi_15_lvs681.gif
A.
Figure 23. Efficiency vs VIN
vo_io_lvs681.gif
A.
Figure 25. DC Output Accuracy VOUT1 = 1.1V
vo_io_18_lvs681.gif
A.
Figure 27. DC Output Accuracy VOUT2 = 1.8V
dc_out_lvs681.gif
A.
Figure 29. DC Output Accuracy VOUT1 = 1.575V,
L = 3.3μH, COUT = 10μF
vo_ripp_lvs681.gif
Figure 31. Output Voltage Ripple In Forced PWM Mode
pwm_pfm_lvs681.gif
Figure 33. Forced PWM/PFM Mode Transition
ld_trns2_lvs681.gif
Figure 35. Load Transient Response PWM Operation
startup_lvs681.gif
Figure 37. Startup Timing One Converter
typ_opr2_lvs681.gif
Figure 39. Typical Operation VIN = 3.6V,
VOUT1 = 1.8V, VOUT2 = 3.0V
vo_easy_sel_lvs681.gif
Figure 41. VOUT1 Change With Easyscale

9.2.2 Various Output Voltages

The TPS6240x is able to be set for different output voltages. Some examples are shown below.

fxd_op_lvs681.gifFigure 42. TPS62401 Fixed 1.575V/1.8V Outputs, Low PFM Voltage Ripple Optimized
fxd_op3_lvs681.gifFigure 43. TPS62401 Fixed 1.575V/1.8V Outputs
fxd_op2_lvs681.gifFigure 44. TPS62401 Fixed 1.1V/1.8V Outputs, Low PFM Ripple Voltage Optimized
circt2_lvs681.gifFigure 45. TPS62403 1.575V/2.8V Outputs

9.2.2.1 Design Requirements

The TPS6240x step-down converter is set to different output voltages.

9.2.2.2 Detailed Design Procedure

See TPS6240x, Dual Outputs Step Down Converter.

9.2.3 Dynamic Voltage Scaling on Converter 1 by DEF_1 Pin

circt1_lvs681.gifFigure 46. Dynamic Voltage Scaling on Converter 1 by DEF_1 Pin

9.2.3.1 Design Requirements

Control the output voltage of the converter 1 through DEF_1 pin by an external processor.

9.2.3.2 Detailed Design Procedure

Connect the DEF_1 pin to the VCore_Sel pin of an external processor, as shown in Figure 46. The processor determines the logic status of the DEF_1 pin which sets the output voltage of the converter 1.

Application Curves

def1_vo_lvs681.gif
Figure 47. TPS62401DEF1_PIN Function For Output Voltage Selection