SLVSCL9A February   2016  – February 2016 TPS62480

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable / Shutdown (EN)
      2. 7.3.2  Soft Start (SS), Pre-biased Output
      3. 7.3.3  Tracking (TR)
      4. 7.3.4  Output Voltage Select (VSEL)
      5. 7.3.5  Forced PWM (MODE)
      6. 7.3.6  Power Good (PG)
      7. 7.3.7  Thermal Good (TG)
      8. 7.3.8  Active Output Discharge
      9. 7.3.9  Undervoltage Lockout (UVLO)
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation (PWM) Operation
      2. 7.4.2 Power Save Mode (PSM) Operation
      3. 7.4.3 Minimum Duty Cycle and 100% Mode Operation
      4. 7.4.4 Phase Shifted Operation
      5. 7.4.5 Phase Add/Shed and Current Balancing
      6. 7.4.6 Current Limit and Short Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Adjustable Output Voltage
        2. 8.2.2.2 Setting VOUT2 Using the VSEL Feature
        3. 8.2.2.3 Output Filter Selection
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 Soft Start Capacitor Selection
        8. 8.2.2.8 Tracking
        9. 8.2.2.9 Current Sharing
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

A recommended PCB layout for the TPS62480 dual phase solution is shown below. It ensures best electrical and optimized thermal performance considering the following important topics:

- The input capacitors must be placed as close as possible to the appropriate pins of the device. This provides low resistive and inductive paths for the high di/dt input current. The input capacitance is split, as is the VIN connection, to avoid interference between the input lines.

- The SW node connection from the IC to the inductor conducts high currents. It should be kept short and can be designed in parallel with an internal or bottom layer plane, to provide low resistance and enhanced thermal behavior.

- The VOUT regulation loop is closed with COUT and its ground connection. To avoid PGND noise crosstalk, PGND is kept split for the regulation loop. If a ground layer or plane is used, a direct connection by vias, as shown, is recommended. Otherwise the connection of COUT to GND must be short for good load regulation.

- The use of thermal (filled) vias underneath the device is recommended for improved thermal performance.

- The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB (and RS pin in case of using R3) pin, avoiding long trace distance.

For more detailed information about the actual 4 layer EVM solution, see SLVUAI6.

10.2 Layout Example

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TPS62480 SLVSCL9_layout.gif Figure 46. TPS62480 Board Layout