SLVSEF9I March   2018  – March 2024 TPS62824 , TPS62824A , TPS62825 , TPS62825A , TPS62826 , TPS62826A , TPS62827 , TPS62827A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse Width Modulation (PWM) Operation
      2. 7.3.2 Power Save Mode (PSM) Operation
      3. 7.3.3 Minimum Duty Cycle and 100% Mode Operation
      4. 7.3.4 Soft Start
      5. 7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Disable, and Output Discharge
      2. 7.4.2 Power Good
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting The Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V , unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = High, no load, device not switching 4 10 µA
IQ Quiescent current EN = High, no load, FPWM devices 8 mA
ISD Shutdown current EN = Low, TJ = -40 ℃ to 85 ℃ 0.05 0.5 µA
VUVLO Under voltage lock out threshold VIN falling 2.1 2.2 2.3 V
Under voltage lock out hysteresis VIN rising 160 mV
TJSD Thermal shutdown threshold TJ rising 150 °C
Thermal shutdown hysteresis TJ falling 20 °C
LOGIC INTERFACE EN
VIH High-level threshold voltage 1.0 V
VIL Low-level threshold voltage 0.4 V
IEN,LKG Input leakage current into EN pin EN = High 0.01 0.1 µA
SOFT START, POWER GOOD
tSS Soft start time Time from EN high to 95% of VOUT nominal, TPS62827 1.75 ms
Time from EN high to 95% of VOUT nominal, TPS62824x/5x/6x/7A 1.25 ms
VPG Power good lower threshold VPG rising, VFB referenced to VFB nominal 94 96 98 %
VPG falling, VFB referenced to VFB nominal 90 92 94 %
Power good upper threshold VPG rising, VFB referenced to VFB nominal 108 110 112 %
VPG falling, VFB referenced to VFB nominal 103 105 107 %
VPG,OL Low-level output voltage Isink = 1 mA 0.4 V
IPG,LKG Input leakage current into PG pin VPG = 5.0 V 0.01 0.1 µA
tPG,DLY Power good deglitch delay PG rising edge 100 µs
PG falling edge 20
OUTPUT
VOUT Output voltage accuracy TPS6282533, PWM mode 3.267 3.3 3.333 V
VOUT Output voltage accuracy TPS6282x18, PWM mode 1.78 1.8 1.82 V
VFB Feedback regulation voltage PWM mode 594 600 606 mV
IFB,LKG Feedback input leakage current for adjustable output voltage VFB = 0.6 V 0.01 0.05 µA
RFB Internal resistor divider connected to FB pin, for fixed output votlage TPS6282518, TPS6282618, TPS6282533 7.5 MΩ
IDIS Output discharge current VSW = 0.4V; EN = LOW 75 400 mA
Load regulation IOUT = 0.5 A to 3 A, VOUT = 1.8 V 0.1 %/A
POWER SWITCH
RDS(on) High-side FET on-resistance 26 mΩ
Low-side FET on-resistance 25 mΩ
ILIM High-side FET switch current limit, DC TPS62824A 1.7 2.1 2.4 A
TPS62825x 2.74 3.3 3.9 A
TPS62826x 3.7 4.3 5.0 A
TPS62827x 4.8 5.6 6.4 A
ILIM Low-side FET negative current limit, DC TPS62824A/5A/6A/7A –1.6 A
fSW PWM switching frequency IOUT = 1 A, VOUT = 1.8 V 2.2 MHz