SLUSEC8A March   2021  – June 2022 TPS628501 , TPS628502 , TPS628503

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Schematic
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable (EN)
      2. 9.3.2 COMP/FSET
      3. 9.3.3 MODE / SYNC
      4. 9.3.4 Spread Spectrum Clocking (SSC)
      5. 9.3.5 Undervoltage Lockout (UVLO)
      6. 9.3.6 Power Good Output (PG)
      7. 9.3.7 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit and Short Circuit Protection
      5. 9.4.5 Foldback Current Limit and Short Circuit Protection
      6. 9.4.6 Output Discharge
      7. 9.4.7 Soft Start
      8. 9.4.8 Input Overvoltage Protection
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 Inductor Selection
      3. 10.1.3 Capacitor Selection
        1. 10.1.3.1 Input Capacitor
        2. 10.1.3.2 Output Capacitor
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Synchronizing to an External Clock
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Description

The TPS62850x is a family of pin-to-pin 1-A, 2-A (continuous), and 3-A (peak) high efficiency, easy-to-use synchronous step-down DC/DC converters. They are based on a peak current mode control topology. Low resistive switches allow up to 2-A continuous output current and 3-A peak current. The switching frequency is externally adjustable from 1.8 MHz to 4 MHz and can also be synchronized to an external clock in the same frequency range. In PWM and PFM mode, the TPS62850x automatically enters power save mode at light loads to maintain high efficiency across the whole load range. The TPS62850x provides a 1% output voltage accuracy in PWM mode, which helps design a power supply with high output voltage accuracy, fulfilling tight supply voltage requirements of digital processors and FPGA.

The TPS62850x is available in an 8-pin 1.60-mm × 2.10-mm SOT583 package.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TPS628501 SOT583 1.60 mm × 2.10 mm (including pins)
TPS628502
TPS628503
For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20200923-CA0I-5J4H-CKNS-KTXQSSRWHPVT-low.gifSimplified Schematic
GUID-20210228-CA0I-D5XL-LHG9-LBSBPCDWQW3N-low.gifEfficiency versus IOUT, VOUT = 3.3 V