SLVSDS9C July   2018  – October 2019 TPS63805 , TPS63806

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application
      2.      Efficiency vs Output Current (VO = 3.3 V)
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions Table
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Control Loop Description
      2. 9.3.2  Precise Device Enable: Threshold- or Delayed Enable
      3. 9.3.3  Mode Selection (PFM/PWM)
      4. 9.3.4  Undervoltage Lockout (UVLO)
      5. 9.3.5  Soft-start
      6. 9.3.6  Adjustable Output Voltage
      7. 9.3.7  Overtemperature Protection - Thermal Shutdown
      8. 9.3.8  Input Overvoltage - Reverse-Boost Protection (IVP)
      9. 9.3.9  Output Overvoltage Protection (OVP)
      10. 9.3.10 Power-Good Indicator
    4. 9.4 Device Functional Modes
      1. 9.4.1 Peak-Current Mode Architecture
        1. 9.4.1.1 Reverse Current Operation, Negative Current
        2. 9.4.1.2 Boost Operation
        3. 9.4.1.3 Buck-Boost Operation
        4. 9.4.1.4 Buck Operation
      2. 9.4.2 Power Save Mode Operation
        1. 9.4.2.1 Current Limit Operation
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Output Capacitor Selection
        4. 10.2.2.4 Input Capacitor Selection
        5. 10.2.2.5 Setting The Output Voltage
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Custom Design With WEBENCH® Tools
      3. 13.1.3 Development Support
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Design Requirements

The design guideline provides a component selection to operate the device within the Table 2.

Table 2 shows the list of components for the application characteristic curves.

Table 2. Matrix of Output Capacitor and Inductor Combinations for the TPS63805

NOMINAL INDUCTOR VALUE [µH](1) NOMINAL OUTPUT CAPACITOR VALUE [µF](2)
10 22 47 66 100
0.47 - + (3) + + +
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
Capacitance tolerance and DC bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
TPS63805 typical application. Other check marks indicate possible filter combinations.

Table 3. Matrix of Output Capacitor and Inductor Combinations for TPS63806

NOMINAL INDUCTOR VALUE [µH](1) NOMINAL OUTPUT CAPACITOR VALUE [µF](2)
10 22 47 66 100
0.47 - - +(1) + +
TPS63806 typical application. Other check marks indicate possible filter combinations.