SLVSCF4A December   2014  – July 2016 TPS650830

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Simplified System Diagram
  2. Revision History
  3. Device Options
  4. Pin Configuration and Functions
    1. 4.1 Pin Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Voltage Regulator Assignment and Powergood Comparator Logic Assignment (External Voltage Regulator or Load Switch) for Skylake and Kabylake Platform
      2. 6.3.2  Generic Powergood Window Comparator with Open-Drain Output
      3. 6.3.3  Powergood Window Comparator
      4. 6.3.4  3.3-V LDO and 3V3SW Load Switch
      5. 6.3.5  5-V LDO and 5VSW Load Switch
      6. 6.3.6  RTC Selector and 3.1-V LDO
      7. 6.3.7  Power Path Comparators
      8. 6.3.8  UVLO Comparators
      9. 6.3.9  Temperature Comparator
      10. 6.3.10 Low Power Mode (LPM) / Connected Standby / Instant Go of VRs
      11. 6.3.11 Enable and Powergood of VRs
      12. 6.3.12 VR4 VDDQ and LDO1 VTT Enabling
      13. 6.3.13 Converters
        1. 6.3.13.1  Power Save Mode
        2. 6.3.13.2  Voltage Regulator Startup
        3. 6.3.13.3  Powergood, Power Fault, and Emergency Power Shutdown
        4. 6.3.13.4  Current Limit
        5. 6.3.13.5  Output Discharge Feature
        6. 6.3.13.6  Output Voltage Control
        7. 6.3.13.7  Converter Low Power Mode Operation
        8. 6.3.13.8  Controller Low Power Mode Operation
        9. 6.3.13.9  Controller Internal Ramp Comparator
        10. 6.3.13.10 Undervoltage Lockout
      14. 6.3.14 Coincell Selector
        1. 6.3.14.1 Functional Description of RTC Powerpath and LDO
    4. 6.4 Device Functional Modes
      1. 6.4.1  OFF State - No VIN and No Backup Battery
      2. 6.4.2  Startup
      3. 6.4.3  Ready State
      4. 6.4.4  S5/S4 State
      5. 6.4.5  S3 State
      6. 6.4.6  S0 State
      7. 6.4.7  Standby
      8. 6.4.8  DSx State
      9. 6.4.9  Emergency Shutdown
      10. 6.4.10 Backup Battery / G3 - No VIN
    5. 6.5 Programming
      1. 6.5.1 I2C - Interface
        1. 6.5.1.1 F/S-Mode Protocol
        2. 6.5.1.2 Diagrams of I2C Protocol
    6. 6.6 Register Map
      1. 6.6.1 Registers
        1. 6.6.1.1  VENDORID Register (address = 0x00) [reset = 00100010]
        2. 6.6.1.2  REVID Register (address = 0x01) [reset = 00000000]
        3. 6.6.1.3  IRQLVL1 Register (address = 0x02) [reset = 00000000]
        4. 6.6.1.4  PWRSRCINT Register (address = 0x04) [reset = 00000000]
        5. 6.6.1.5  PMUINT Register (address = 0x05) [reset = 00000000]
        6. 6.6.1.6  RESETIRQ1 Register (address = 0x08) [reset = 00000000]
        7. 6.6.1.7  RESETIRQ2 Register (address = 0x09) [reset = 00000000]
        8. 6.6.1.8  MPMUINT Register (address = 0x0B) [reset = 00010100]
        9. 6.6.1.9  MPWRSRCINT Register (address = 0x0C) [reset = 01111000]
        10. 6.6.1.10 RESETIRQ1MASK Register (address = 0x11) [reset = 00110000]
        11. 6.6.1.11 RESETIRQ2MASK Register (address = 0x12) [reset = 00000010]
        12. 6.6.1.12 IRQLVL1msK Register (address = 0x13) [reset = 10100101]
        13. 6.6.1.13 PBCONFIG Register (address = 0x14) [reset = 00011111]
        14. 6.6.1.14 PBSTATUS Register (address = 0x15) [reset = 00000000]
        15. 6.6.1.15 PWRSTAT1 Register (address = 0x16) [reset = 00000000]
        16. 6.6.1.16 PWRSTAT2 Register (address = 0x17) [reset = 00000000]
        17. 6.6.1.17 PGMASK1 Register (address = 0x18) [reset = 00000000]
        18. 6.6.1.18 PGMASK2 Register (address = 0x19) [reset = 00000000]
        19. 6.6.1.19 VCCIOCNT Register (address = 0x30) [reset = 00001010]
        20. 6.6.1.20 V5ADS3CNT Register (address = 0x31) [reset = 00101010]
        21. 6.6.1.21 V33ADSWCNT Register (address = 0x32) [reset = 00101010]
        22. 6.6.1.22 V33APCHCNT Register (address = 0x33) [reset = 00001010]
        23. 6.6.1.23 V18ACNT Register (address = 0x34) [reset = 00101010]
        24. 6.6.1.24 V18U25UCNT Register (address = 0x35) [reset = 00001010]
        25. 6.6.1.25 V1P2UCNT Register (address = 0x36) [reset = 00111010]
        26. 6.6.1.26 V100ACNT Register (address = 0x37) [reset = 00011010]
        27. 6.6.1.27 V085ACNT Register (address = 0x38) [reset = 00101010]
        28. 6.6.1.28 VRMODECTRL Register (address = 0x3B) [reset = 00111111]
        29. 6.6.1.29 DISCHCNT1 Register (address = 0x3C) [reset = 00000000]
        30. 6.6.1.30 DISCHCNT2 Register (address = 0x3D) [reset = 00000000]
        31. 6.6.1.31 DISCHCNT3 Register (address = 0x3E) [reset = 00000000]
        32. 6.6.1.32 DISCHCNT4 Register (address = 0x3F) [reset = 00000000]
        33. 6.6.1.33 PWRGDCNT1 Register (address = 0x40) [reset = 01011111 ]
        34. 6.6.1.34 VREN Register (address = 0x41) [reset = 00000000]
        35. 6.6.1.35 REGLOCK Register (address = 0x42) [reset = 00000000]
        36. 6.6.1.36 VRENPINMASK Register (address = 0x43) [reset = 00000000]
        37. 6.6.1.37 RSTCTRL Register (address = 0x48) [reset = 00011100]
        38. 6.6.1.38 SDWNCTRL Register (address = 0x49) [reset = 00000000]
        39. 6.6.1.39 VDLMTCRT Register (address = 0x51) [reset = 00000101]
        40. 6.6.1.40 ACOKDBDM Register (address = 0x69) [reset = 00001111]
        41. 6.6.1.41 LOWBATTDET Register (address = 0x6A) [reset = 11111000]
        42. 6.6.1.42 SPWRSRCINT Register (address = 0x6F) [reset = 00000000]
        43. 6.6.1.43 CLKCTRL1 Register (address = 0xD0) [reset = 00000000]
        44. 6.6.1.44 COMPA_REF Register (address = 0xDD) [reset = 00000000]
        45. 6.6.1.45 COMPB_REF Register (address = 0xDE) [reset = 00000000]
        46. 6.6.1.46 COMPC_REF Register (address = 0xDF) [reset = 00000000]
        47. 6.6.1.47 COMPD_REF Register (address = 0xE0) [reset = 00000000]
        48. 6.6.1.48 COMPE_REF Register (address = 0xE1) [reset = 00000000]
        49. 6.6.1.49 COMPF_REF Register (address = 0xE2) [reset = 00000000]
        50. 6.6.1.50 COMPG_REF Register (address = 0xE3) [reset = 00000000]
        51. 6.6.1.51 COMPH_REF Register (address = 0xE4) [reset = 00000000]
        52. 6.6.1.52 PWFAULT_MASK1 Register (address = 0xE5) [reset = 00000000]
        53. 6.6.1.53 PWFAULT_MASK2 Register (address = 0xE6) [reset = 00000000]
        54. 6.6.1.54 PGOOD_STAT1 Register (address = 0xE7) [reset = 00000000]
        55. 6.6.1.55 PGOOD_STAT2 Register (address = 0xE8) [reset = 00000000]
        56. 6.6.1.56 MISC_BITS Register (address = 0xE9) [reset = 00010000]
        57. 6.6.1.57 STDBY_CTRL Register (address = 0xEA) [reset = 11111110]
        58. 6.6.1.58 TEMPCRIT Register (address = 0xEB) [reset = 00000000]
        59. 6.6.1.59 TEMPHOT Register (address = 0xEC) [reset = 00000000]
        60. 6.6.1.60 VREN_PIN_OVR Register (address = 0xEE) [reset = 00000000]
  7. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Controller Design Procedure
          1. 7.2.2.1.1 Selecting the Inductor
          2. 7.2.2.1.2 Selecting the Output Capacitors
          3. 7.2.2.1.3 Selecting the FETs
          4. 7.2.2.1.4 Bootstrap Capacitor
          5. 7.2.2.1.5 Setting the Current Limits
          6. 7.2.2.1.6 Selecting the Input Capacitors
        2. 7.2.2.2 Converter Design Procedure
          1. 7.2.2.2.1 Selecting the Inductor
          2. 7.2.2.2.2 Selecting the Output Capacitors
          3. 7.2.2.2.3 Selecting the Input Capacitors
        3. 7.2.2.3 LDO Design Procedure
        4. 7.2.2.4 Board Temperature Monitoring Design Procedure
        5. 7.2.2.5 Power Path Design Procedure
      3. 7.2.3 Application Performance Curves
      4. 7.2.4 Specific Application - TPS650830 Powering the Intel SkyLake and Kabylake Platform Volume Configuration
        1. 7.2.4.1 Design Requirements
        2. 7.2.4.2 Detailed Design Procedure
          1. 7.2.4.2.1 Output Inductance and Capacitance
        3. 7.2.4.3 Application Performance Curves
    3. 7.3 System Example
    4. 7.4 Do's and Don'ts
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Fanout for ZAJ using Type 4 Routing
      2. 9.1.2 Fanout for ZCG using Type 3 Routing
      3. 9.1.3 Layout Checklist
    2. 9.2 Layout Example
      1. 9.2.1 Controller Layout
      2. 9.2.2 ZAJ Package
      3. 9.2.3 ZCG Package
    3. 9.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Detailed Description

6.1 Overview

The TPS650830 is a single-chip solution Power Management IC designed specifically for the latest Intel Processors targeted for Tablets, Ultrabooks, and Notebooks with NVDC or non-NVDC power architectures, using 2S, 3S, or 4S Lithium-Ion battery packs.

The TPS650830 is used for Volume systems with the low voltage rails merged for the smallest footprint and lowest cost system power solution.

The TPS650830 can provide the complete power solution based on the Intel Reference Designs. Five highly efficient step-down voltage regulators (VRs) and a sink/source LDO, are used along with power-up sequence logic managing external load switches to provide the proper power rails, sequencing, and protection - including DDR3 and DDR4 memory power. The regulators support dynamic voltage scaling (DVS) for maximum efficiency including Connected Standby. The high frequency voltage regulators use small inductors and capacitors to achieve a small solution size. Output power is adjustable on four VR controllers. An I2C interface allows simple control by the embedded controller (EC). Each version is available in a 7x7 NFBGA package and a 9x9 NFBGA package. The 7x7 NFBGA package can be used in Type 4 PCB boards for the smallest area implementation. The 9x9 NFBGA package can be used in Type 3 and Type 4 PCB boards allowing to minimize cost and area.

The Powergood Comparator Logic allows controlling and monitoring up to eight external load switches within the sequence. All the VR and Load Switch Powergood signals are used in the Powergood Tree of which the outputs are shown with open-drain outputs. Enable inputs allow connecting externally to set the sequence, and it also allows using various Sleep Mode State signals. The STANDBYZ allows entering a Deep Sleep Mode, in which the out put voltages of the voltage regulators can be reduced to save power by DVS.

The Power Monitoring comparators are used to detect and monitor up to three input power sources (adapter, battery1, battery2, or any other combination). Over temperature of the PMIC self-protects, and outputs a Status output, TEMPALERTZ; plus there is a dedicated comparator that can monitor system over temperature with multiple stacked PTC thermistors, or an NTC thermistor. The PMIC automatically switches between an internal 3.1-V LDO when a power source is connected; or to a Backup Battery (Coin Cell) when all power sources are removed. This output RTC rail is used to maintain the always-on RTC rails for critical register data.

6.2 Functional Block Diagram

TPS650830 TPS650830_SLVSCF4_block_diagram.gif

6.3 Feature Description

6.3.1 Voltage Regulator Assignment and Powergood Comparator Logic Assignment (External Voltage Regulator or Load Switch) for Skylake and Kabylake Platform

For the Skylake and Kabylake Power Map implementation, the five PMIC voltage regulators and LDO1 are assigned with the low -voltage rails merged or split according to the configuration. For the Volume (merged low voltage rails) configuration six external load switches are controlled and monitored by using six powergood comparator logic blocs.

Table 6-1 Voltage Regulator and Powergood Comparator Logic Assignment for Skylake and Kabylake Platforms

TPS650830 Skylake and Kabylake PLATFORM POWER
SYSTEM VOLTAGE RAIL
VOLUME (Merged Low Voltage Rails)
OUTPUT VOLTAGE, Vout DEFAULT, or COMPARATOR INPUT SWITCHING FREQUENCY, Fsw
NVDC# = 1 / 0
LPM VOLTAGE, Vout
DEFAULT
POWER GOOD OUTPUT SETTING, (PGVRx or PGx is PP or OD)
VR1 V1.00A / V0.85A 1.00 V 500 kHz / 800 kHz LPM = 1.00 V PP
VR2 V1.8A 1.8 V 2 MHz / 2 MHz LPM = 1.8 V PP
VR3 V3.3A_DSW 3.3 V 800 kHz / 800 kHz LPM = 3.3 V PP
VR4 V1.2U 1.2 V,1.35 V,1.1 V 500 kHz / 800 kHz LPM = 1.2 V,1.35 V,1.1 V OD
VR5 V5A_DS3 5 V 800 kHz / 800 kHz LPM = 5.0 V PP
LDO1 V0.6Dx 0.6 V, 0.675 V, 0.55 V - LPM = DDR_VTT_CTRL = Off NA
External VR_a none - - - NA
External VR_b none - - - NA
Powergood Comparator Logic a V3.3A_PCH Enable/Sense External Load Switch 3.3 V, Comparator Analog Input PP
Powergood Comparator Logic b V1.8U_2.5U Enable/Sense External Load Switch 1.8 V, Comparator Analog Input PP
Powergood Comparator Logic c Generic Comparator - --
Powergood Comparator Logic d VCCIO Enable/Sense External Load Switch 1.00 V, Comparator Analog Input PP
Powergood Comparator Logic e V3.3S Sense External Load Switch 3.3 V, Comparator Analog Input PP
Powergood Comparator Logic f V1.8S Sense External Load Switch 1.8 V, Comparator Analog Input PP
Powergood Comparator Logic g V1.0S Sense External Load Switch 1.00 V, Comparator Analog Input OD

6.3.2 Generic Powergood Window Comparator with Open-Drain Output

The generic powergood comparator monitors the output voltage to ensure it is within ±10% of the nominal target voltage there is a 30-µs deglitch on both rising and falling edges of all comparators (converter, controller, comparators). The open-drain output requires an external pull-up resistor - typically in the 100-kΩ range. Open-Drain outputs can be combined to create an "AND" logic function.

TPS650830 24_PwrGd_Detail.gif Figure 6-1 Generic Powergood Window Comparator with Open-Drain Output

6.3.3 Powergood Window Comparator

All the powergood comparators (converter, controller, comparators) can be configured for either Open-Drain outputs or Push-Pull outputs.

All the powergood comparators (converter, controller, comparators) in analog configuration monitors the output voltage to ensure it is within ±10% of the nominal target voltage. A 30-µs deglitch exists on the output of all the powergood comparators (converter, controller, comparators). The open-drain output requires an external pull-up resistor - typically in the 100-kΩ range. Open-Drain outputs can be combined to create an "AND" logic function. The push-pull output internally pulls up to VDDIO pin rail, or other noted input rail. Care should be taken to minimize series impedance on the PCB and providing adequate bulk and decoupling capacitance for the load switch rails. The Intel Skylake and Kabylake specification is ±5% at each rail, including those provided by load switches, therefore the load switch rails are still protected for ±10% powergood, as required by Intel Skylake and Kabylake specification.

TPS650830 09_Pwrgd_Wndw_Comp_OD.gif Figure 6-2 Powergood Window Comparator with Open-Drain Output
TPS650830 10_Pwrgd_Wndw_Comp_PP.gif Figure 6-3 Powergood Window Comparator with Push-Pull Output

6.3.4 3.3-V LDO and 3V3SW Load Switch

The LDO3V powers up when Vin_LDO3V pin goes above the UVLO3V threshold. The LDO3V powers the internal digital blocks and analog blocks of the PMIC. It is also used as the positive rail of the powergood comparator and level-shifter outputs. The 3V3 load switch is optional to connect or disconnect the VOUT3V3SW output to a load. The load switch is enabled by the EN3V3SW pin.

TPS650830 11_LDO3_and_LDSW.gif Figure 6-4 LDO3V and 3V3SW Load Switch

6.3.5 5-V LDO and 5VSW Load Switch

The LDO5V powers up when Vin pin goes above the UVLO5V threshold. The LDO5V powers the gate drives for all the five VRs of the PMIC. The 5-V load switch is used to switch the gate drive source from the internal LDO5V LDO to the 3.3-V PWM VR output as soon as the 3.3-V VR powergood signal indicates it is good. This significantly improves the efficiency of the VRs whose effect is more significant at lower VR load current, and VR input voltage. The load switch is enabled by the EN5VSW pin. Connect the V5A_PG signal to the EN5VSW pin. When the EN5VSW pin is high, the LDO5V internal reference drops to 4.5 V to ensure the 5-V VR drives all the gate drive current, but also ensures the gate drive never falls below 4.5 V. When EN5VSW is low, the LDO resumes to 5-V internal reference and the load switch is turned off to disconnect the 5-V VR.

TPS650830 12_LDO5_and_LDSW.gif Figure 6-5 5-V LDO and 5VSW Load Switch

6.3.6 RTC Selector and 3.1-V LDO

The RTC selector is used to select between the coincell backup battery or the internal 3.3-V LDO to power the 3P3A_RTC output rail for the RTC domain rail. If the Vin is below the UVLo5V threshold, the coincell battery is selected. If the Vin is greater than the UVLO5V, then the internal 3.1-V LDO is selected. The backup battery selector logic has a very low current draw when battery is selected to extend the charge life of the backup battery. This rail allows keeping the RTC registers' data even when the adapter and main battery is removed from the system. If the coincell voltage falls below the minimum threshold, the RTC registers will be reset to the default values. The 3.1-V LDO is at 3.1 V to ensure the PCH voltage is always below 3.2 V maximum to protect the PCH.

TPS650830 13_RTC_Selector_3p1vLDO.gif Figure 6-6 RTC Selector and 3.1-V LDO

6.3.7 Power Path Comparators

The Power Path comparators are high voltage comparators rated at 28 V both input and output that are independent of the rest of the PMIC. These can be used even when the PMIC is powered down, as long as the VINPP pin is above the UVLO5V threshold. Connect a resistor divider from the source to set the 1.25-V trigger threshold. These comparators can be used to detect adapter, and up to two batteries. An open-drain pin can detect the status, and a status register detects the status, that can issue an interrupt to the EC. The high voltage rated outputs can be used to turn on external P-channel power MOSFETs to control the power source path. A diode "OR" connection from all the power sources used is recommended to ensure the VINPP is up when a source is available. If these comparators are not used tie the VINPP pin to VIN and VIN_LDO3. Do not ground the VINPP pin when the VIN pin is powered up. These comparators can also be used a general purpose comparators.

TPS650830 14_Pwr_Path_Comps.gif Figure 6-7 Power Path Comparators

6.3.8 UVLO Comparators

The UVLO comparators are high voltage comparators rated at 28-V input are powered by the VIN pin for LDO5V and 1.25-V LDO, and the VIN_LDO3V pin for th LDO3V. The VDCSNS input is also a high voltage input pin to detect if VBATA is above a programmable voltage. The Vin and VIN_LDO3 pin are tied directly to VBATA, while the VDCSNS pin requires a resistor divider to set the proper detection gain.

TPS650830 15_UVLO_Comps.gif Figure 6-8 UVLO Comparators

6.3.9 Temperature Comparator

The temperature comparator is used to detect either several PTC thermisters stacked in series string, or a single NTC thermister. The PTC thermisters allow an inexpensive overtemperature detection of any fault throughout several points on the motherboard with each PTC thermister selected to have its own temperature threshold trigger point. An internal current source can be enabled to drive the PTC thermisters to minimize noise sensitivity. The current source can be disabled to drive with a voltage source such as the LDO3V to allow a tighter accuracy. Only a single NTC thermister can be detected at a time, but the NTC allows tracking several temperature profiles. This comparator can also be used as a general purpose comparator.

TPS650830 16_Temp_Comp.gif Figure 6-9 Temperature Comparator

6.3.10 Low Power Mode (LPM) / Connected Standby / Instant Go of VRs

All the Voltage regulators from the PMIC can be programmed by register to change the voltage in active mode, or to change to a lower voltage or decay in the low power mode. This can be used to save system power and extend battery life. And such capability is useful to meet the Connected Standby and Instant Go specifications. The STANDBYZ pin triggers low power mode (LPM) when low. The STANDBYZ triggers active mode (not in LPM) when high. Connect the SLP_S0# signal from the PCH to the STANDBYZ pin to trigger the low power mode, LPM. The default settings can be changed by the user with the I2C register at any time.

TPS650830 17_Connected_Standby_InstantGO_VRs.gif Figure 6-10 Low Power Mode (LPM) / Connected Standby / Instant Go of VRs
TPS650830 DVS_Transition_2.gif Figure 6-11 Dynamic Voltage Scaling (DVS) Transition Timing

The DVS Timing is controlled by the stepping the internal reference down/up. The total ramp down/up transition time is equal to the step time times the number of steps. The number of steps is equal to [(the VOUT_hi voltage minus the VOUT_lo voltage) divided by 25 mV per step]. The step time of 5 µs per 25-mV step ensures a time less than 70 µs for a 300-mV voltage change. The Controller is forced in PWM from the STANDBY# (LPM) transition until 10 µs after the reference ramp down/up ends. This helps ensure a fast response. Likewise the Powergood signal for that rail is masked from the STANDBY# (LPM) transition until 100 µs after the internal reference ramp down/up ends. This ensures there is no false powergood fault turn-off during DVS. In most cases undershoot/overshoot is negligible.

6.3.11 Enable and Powergood of VRs

The VRs are enabled by the ENVRx pins. The powergood is output on the PGVRx pins. The powergood pins can be defined as open-drain or push-pull output, depending on the function in order to allow "ANDing" or to reduce external components and quiescent current. there is a 30-µs deglitch on both edges of the powergood comparator outputs. A status register monitors the powergood outputs, and the powergood tree monitors the powergood for proper sequence and protection. The powergood signals can be masked by a register.

TPS650830 18_Ena_Vout_Pwrgd.gif Figure 6-12 Enable and Powergood of VRs

6.3.12 VR4 VDDQ and LDO1 VTT Enabling

The VDDQ is enabled by the ENVR4 pin, while the LDO1 VTT push-pull LDO is enabled by the DDR_VTT_CTRL pin. The DDR_VTT_CTRL pin is often connected to the SLP_S0# pin to turn off during sleep mode. The DDRID pin is a tri-level pin that sets the VR4 VDDQ voltage to either 1.2 V, 1.35 V, or 1.1 V. DDR_VTT_CTRL pin ais also used for DVS control of VR4, as defined on register 0x36, V1P2UCNT.

TPS650830 19_LDO1_EN.gif Figure 6-13 VR4 VDDQ and LDO1 VTT Enabling

6.3.13 Converters

The PMIC has 5 built in DCDC converters. The voltage regulators are highly configurable both in terms of voltage and current. Of the five voltage regulators, four voltage regulators have an external power stage, with programmable current limit (programmed by an external resistor), which allows optimal selection of external passive components based on desired system load. VR2 has a completely integrated power stage, except for the required passive components. To maintain high efficiency, the converters are implemented as synchronous step down converters.

One additional voltage regulators in the form of Low Drop Out (LDO) linear regulators are integrated as part of the PMIC. One of the LDOs, LDO1, is capable of sinking and sourcing current that regulates from the step down controller (for DDR memory). This LDO is designed to specifically provide the VTT power to DDR memory. Its output voltage tracks the output voltage of the step down controller and is set to regulate to half of the step down controller voltage.

6.3.13.1 Power Save Mode

At medium and heavy loads, the converter and the controllers operate in a PWM mode. As soon as the inductor current gets discontinuous, which means that the output current gets lower than half of the inductor ripple current, the converters enter Power Save Mode. In Power Save Mode the switching frequency decreases linearly with the load current and maintains a high efficiency. By default, the converters and controller operate in the AutoPFM mode such that the transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in both directions.

TPS650830 psmt_LVSC78.gif Figure 6-14 PFM and PWM Mode Operation

The figure above shows the converter/ controller operation in PFM and PWM mode. In PFM mode the minimum voltage that the output falls to is the programmed regulation voltage. The output voltage ripple in PFM mode is determined based on the external passive components (L and C). The regulator ensures that the minimum voltage during PFM mode is the same as the programmed regulation voltage (within the AC and DC tolerance).

TPS650830 24_16_pulse_CCM_to_DCM_Transition_2.gif Figure 6-15 Operation During Load Step Transient: CCM to DCM Transition and DCM to CCM Transition

The figure above shows the inductor current of the controller during a load transient as it transitions in and out of Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). CCM is often referred to as pulse width modulation (PWM) mode, and DCM is referred to as pulse frequency mode (PFM) mode. When the load step falls, there is a 16 cycle deglitch going from CCM to DCM. This allows a fast transient response and tighter peak to peak ripple voltage. When the load step rises, there is no deglitch time, so the controller goes directly from DCM to CCM in a quick response characteristic of CCM. The VR1, VR3, VR4, and VR5 controllers have the CCM to DCM 16 cycle count deglitch enabled.

6.3.13.2 Voltage Regulator Startup

All the voltage regulators including the VTT LDO1 can be enabled using either pin enables or I2C commands. The default setting uses the pin enable. The VTT LDO1 can only be enabled using the DDR_VTT_CTRL discrete input. VTT LDO1 can be enabled by pin (DDR_VTT_CTRL) or by register (0xE9, MSB bit 7 masks the DDR_VTT_CTRL pin, and bit 6 enables the VTT LDO1). Each Voltage Regulator (VR) can be enabled by the enable pin (ENAVRx) or by I2C Register (xCNT). The voltage should not be changed by register at the exact same time the voltage regulator is enabled. If a different voltage than the default is needed at power-up, then the register (xCNT) should program the voltage first, and then a separate command should enable the register separately. Dynamic voltage change (DVS) can be done any time after power-up.

Each of the voltage regulators except for the VTT LDO1 are controlled by an internal softstart to make sure the output voltage ramps up gently and does not cause huge inrush current during startup to prevent droop on the input. The VTT LDO1 startup time is driven by the DDR memory requirements for the VTT voltage rail - which requires that the ramp up on voltage be faster than 35 µs.

6.3.13.3 Powergood, Power Fault, and Emergency Power Shutdown

During operation, when the voltage regulators are enabled, the output voltage for each rail is monitored in order to assess if the output voltage is within a specified voltage range. A powergood status bit is generated and stored in the PGOOD_STAT1 and PGOOD_STAT2 registers. If the output voltage is within the specified voltage range, the respective powergood status bit is set to a logic high. If the output voltage falls below or goes above the specified voltage range, the powergood status bit will be set to a logic low.

By default, if any of the output voltage rails experience a power fault condition, the PMIC will automatically shutdown in order to protect the system unless the power fault is masked. If a power fault occurs, the source of the power fault is maintained in the PWRSTAT1 and PWRSTAT2 registers which are maintained in the RTC domain. The voltage thresholds for each of the powergood comparators is a percentage relative to the nominal voltage setting of the output voltage - see the parametric table for each voltage regulator powergood for the USL and LSL limits of the powergood comparators.

If a particular voltage rail is not critical to the performance of the overall system, the respective powergood output can be masked using the PGMASK1 and PGMASK2 registers. The masking of a power fault will inhibit an automatic PMIC shutdown. This can be also very helpful for debug purposes in case of system failure to isolate the voltage regulator with the sensitive output voltage.

In order to avoid an erroneous power fault during the turn-on of the voltage regulators, the power fault is masked for 10 ms relative to the enable whether it be from the discrete signal or from an I2C command. powergood is also masked when coming out of sleep (S3 state) for 100 µs after the ALL_SYS_PWRGD pin goes high to ensure that there is no false triggering of the powergood comparators.

The PMIC will only cause a Emergency Power Shutdown of the rails for the conditions shown in the table below. The PMIC monitors each rail and ensures there is no problem. All rails are monitored for fault protection, except for V3.3A_DSW and V5A external voltage regulators. The V3.3A_DSW and V5A have no effect on Power Fault and cannot cause a shutdown, unless either one affects another rail. Notice also, that the current limit (OCP) does not directly cause a shutdown. Instead, OCP could cause a shutdown indirectly by means of a Power Fault. The OCP will limit the maximum possible output current, such that if the load current exceeds the Ilim, then the voltage will drop, until eventually the lower output voltage causes a Power Fault if it is below the powergood threshold for more than 30 µs. Emergency Power Shutdown causes all rails to power-down within 1 us. The LDO3, LDO5, and VREF1.25V will stay up if the input voltage is greater than the UVLO3 and UVLO5.

Table 6-2 All Possible Emergency Power Shutdown Conditions

SHUTDOWN CONDITION
VIN pin ≤ UVLO5V
VINLDO3 pin ≤ UVLO3V
Powergood Fault (OVP, UVP): Vout ≤ 90% or Vout ≥ 110% for ≥ 30 µs
Tj ≥ Tcritical (OTP)
SHUTDOWNZ pin pulled-low
I2C Control Force Shutdown by SDWNCTRL register (address = 0x49)

6.3.13.4 Current Limit

All voltage regulators are current limited, the current limit can be set based on the application load current using an external resistor for all VRs except for VR2 which has an internally set current limit as it has an integrated power stage. The current limit controls the maximum output current. If the maximum current is reached, the output voltage will start to droop since the load can no longer be supplied with sufficient power. If the voltage drops below the powergood threshold, the power fault status will be set to a logic high and if the power fault is not masked, the PMIC will automatically shutdown in a controlled manner to protect the system.

6.3.13.5 Output Discharge Feature

All the voltage regulators have a built in output discharge feature. The output discharge feature consists of being able to configure register bits to enable a discharge resistor which is only active whenever the voltage regulator is disabled. The discharge resistors for each of the voltage regulators can be configured using the DISCHCNT1, DISCHCNT2, DISCHCNT3 and DISCHCNT4 registers. The discharge resistors are disconnected when the voltage regulators are enabled in order to minimize any losses within the PMIC.

6.3.13.6 Output Voltage Control

All voltage regulators are designed to regulate a fixed output voltage. To achieve high accuracy the output voltage for the converters and controller is sensed using a separate feedback pin. For each of the voltage rails, except for the VTT LDO, the output voltage can be changed to slightly higher or lower values by changing the default setting in the voltage regulator control registers (see section on the Voltage Regulator Voltage Options). This function can be used to save power when supplying the connected load at its minimum possible supply voltage or to compensate for voltage drops during load transients by programming it slightly higher. In addition the range of the output voltage for the regulators is highly programmable. If you need a different output voltage configuration from the specified default, please contact TI to generate you a custom part.

6.3.13.7 Converter Low Power Mode Operation

For optimizing low power operation, the output voltage of the converters can be set to a specific value. The low power output voltage is set by the specific register and bits shown in the Voltage Regulator Voltage Options tables. Entering the low power mode is accomplished by asserting the SLP_S0# signal to a logic low. In this low power mode, the powergood function remains active and is not affected by the transition from normal operation mode to the low power mode and vice versa.

6.3.13.8 Controller Low Power Mode Operation

For optimizing low power operation, the output voltage of the controllers can be set to a specific value. The low power output voltage is set by the specific register and bits shown in the Voltage Regulator Voltage Options tables. Entering the low power mode is accomplished by asserting the DDR_VTT_CTRL pin or the STANDBYZ pin to a logic low. In this low power mode, the powergood function remains active and is not affected by the transition from normal operation mode to the low power mode and vice versa. DDR_VTT_CTRL pin asserts DVS on VR4, while STANDBYZ pin asserts DVS in VR1, VR2, VR3, and VR5, as defined by ther CNT registers. In situations where the output current demand from the controller is very small, the controller is automatically placed in an Ultra Low Quiescent (ULQ) mode to reduce power consumption and increase the efficiency.

6.3.13.9 Controller Internal Ramp Comparator

The controllers have an internal ramp, characteristic of th DCAP2 control architecture, to give improved performance with low-ESR output capacitors. This internal ramp provides ramp compensation that helps maintain a relatively constant frequency during CCM, and it provides better stability for designs with very low ESR on the output capacitors. The ramp height can be optimized and is a function of the input voltage to provide proportional feed-forward. At very high voltages, the ramp may exceed the operating window of the PWM comparator and may overpower the natural ripple of the output, so there is a need to switch to a smaller ramp. As the ramp was already getting large, it helps to switch back to a smaller size. To achieve this, a comparator monitors the input voltage at the VIN pin. When input voltage rises and exceeds 11 V, it changes the ramp to a slightly smaller value. There is a wide 1.1-V hysteresis, so at approximately 9.9 V as the Vin falls, the ramp returns to the slightly bigger size. In most cases this difference is negligible.

6.3.13.10 Undervoltage Lockout

An undervoltage lockout function prevents the PMIC from operating if the supply voltage on the VIN pin of the PMIC is lower than the undervoltage lockout threshold (see Electrical Characteristics table). During operation, if the supply voltage on the VIN pin drops below the undervoltage lockout threshold, the system/PMIC will shutdown.

6.3.14 Coincell Selector

6.3.14.1 Functional Description of RTC Powerpath and LDO

In case where the main system battery is removed and there is no alternate power source, the RTC data, configuration and status registers, oscillator and timekeeping path of the RTC block are backed up by either a super capacitor or a coin cell battery. If the coincell/ super capacitor battery voltage falls below the minimum operational voltage and there is no input voltage (AC/ DC above the PMIC UVLO), the RTC data registers will be invalid. As the Intel RTC cannot handle a max voltage higher than 3.2 V, when AC/DC is present and is higher than the UVLO threshold, the RTC is supplied by the AC/DC rather than from the coincell - thus maximizing the stored charge in the coincell battery. When AC/DC is present, the internal coincell selector selects the higher of the coincell voltage and the AC/DC voltage. When AC/DC is chosen as a source, there is a coincell LDO which is driven from the 5-V PMIC LDO to regulate The output voltage is fixed at 3.1 V to ensure the maximum voltage is kept below 3.2 V.

The main power source for the RTC LDO is the 5-V PMIC internal LDO, when the main system battery (VDC) is greater than 5.4 V. The RTC LDO will be bypassed and the RTC supply will be powered by the coincell when VDC falls below this threshold - to maximize the coincell battery life. The coincell is used as a last resort. All power routing of the source selection for the RTC power is done internally and no external connections other than the coin cell or super cap is required.

6.4 Device Functional Modes

TPS650830 StateDiagram830.gif Figure 6-16 Sequence of Function Modes - Assuming the TPS650830 Application Configuration Connections

6.4.1 OFF State - No VIN and No Backup Battery

If the VIN and the VBATTBKUP battery are both lower than their respective UVLOs then, the device will be in the OFF state. In this state the device will not be able to turn on or enable any VRs or discrete load switches / regulators. The clock and I2C are not active in this state.

In the OFF state, the power path switch comparators, ACIN, BAT1, and BAT2 are the only block available for use. In order to use these comparators the VINPP must be supplied with the highest of the 3 input voltages from AC, BAT1, and BAT2. In all other states the VINPP must be supplied from the same source as VIN.

6.4.2 Startup

The device enters STARTUP once the VIN > UVLO. During STARTUP LDO3V, LDO5V, and VREF1V25 ramp up. Once both LDO3V and LDO5V reach their nominal voltage and their powergoods assert HIGH, the OTP loads into the I2C registers. After the LDO5V_PG asserts HIGH, the RTC LDO is turned on and the V3.3A_RTC is regulated to 3.1 V powered from the LDO5V. Once the OTP is loaded and the RTC is regulated to 3.1 V the device enters READY state.

6.4.3 Ready State

The device is considered to be in the READY state once, all of the internal supplies and RTC are regulated and the OTP is loaded into the registers. In this state the device is ready for enable commands. The comparators, level shifters and all other blocks are available for use.

6.4.4 S5/S4 State

The S5/S4 states are entered when the V3.3A_DSW, V1.8A, V5A_DS3, V3.3A_PCH, V0.85A, and V1.00A are all enabled and regulating with valid powergoods. In this state the RSMRST#_PWRGD will be asserted HIGH.

6.4.5 S3 State

To enter S3 state the SLP_S4# signal must be asserted HIGH. Upon SLP_S4# assertion the VDDQ (VR4), and V1.8U rails are turned on.

6.4.6 S0 State

To enter S0 state the SLP_S3# signal must be asserted HIGH in addition to valid 3.3-V, 1.8-V, and 1.0-V signals on VSE, VSF, and VSG pins. Upon PGG = 1 and PGVR4 = 1 the VCCIO and rail is turned on and the device transitions to S0 state. ALL_SYS_PWRGD asserts HIGH in this state.

6.4.7 Standby

Standby is entered when the STANDBYZ pin transitions from HIGH to LOW provided that ALL_SYS_PWRGD is HIGH. During the STANDBY state the device will DVS and/or decay the VRs that are programmed to DVS or decay from the I2C register definitions, (registers x30 - x38).

6.4.8 DSx State

The DSx state is entered from STARTUP by the enabling of V3.3A_DSW. From the S5/S4 states it can be entered by either pulling the SLP_SUS# signal LOW or writing to VREN, EC_SLP_S4 = EC_DS4 = 1. In this state, the V5A_DS3 and V1.8A may be turned off.

6.4.9 Emergency Shutdown

Emergency Shutdown is a protection feature for the system loads. It reduces the risk of reverse bias in the processor or other devices from once rail to another. Once Emergency Shutdown is initiated the DPWROK pin is pulled LOW, discharge resistors are enabled for all rails, and all rails are disabled at the same time. The PMIC remains in Emergency Shutdown until any of the follow occurs:

  • PWRBTNIN falling edge detected
  • ACOK transitions from LOW to HIGH
  • VIN < UVLO

Emergency Shutdown is initiated when:

  • VR Fault detected - Read RESETIRQ1 to determine if VR fault caused shutdown.
  • Hardware force shutdown
  • Software force shutdown
  • Die Thermal Fault - Read RESETIRQ2 to determine if thermal fault caused shutdown.
  • PWRBTN held longer than defined time by FLT[5:0] - Read RESETIRQ1 to determine if push button caused shutdown.
  • VIN < UVLO - Read IRQLVL1 bit 2 to determine if VIN < UVLO caused shutdown.

6.4.10 Backup Battery / G3 - No VIN

G3 is an Intel defined state where the VIN < UVLO to the device but, a valid backup battery is present on VBATTBKUP pin. In this state, the backup battery is passed to the RTC output and the RTC domain I2C register values are saved. Once the VIN > UVLO these register retain their value and can be read once I2C is ready.

In this state, all VRs and internal LDOs are off and I2C access is not available.

6.5 Programming

6.5.1 I2C - Interface

I2C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I2C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The TPS650830 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents are loaded when voltage is applied to TPS650830 higher than the undervoltage lockout threshold. The I2C interface is running from an internal oscillator that is automatically enabled when there is an access to the interface.

The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as F/S-mode in this document.

The TPS650830 supports 7-bit addressing; 10-bit addressing and general call address are not supported. The default device address is defined by the status of the SLAVEADDR pin. 3 different slave addresses are possible, 0x30 (SLAVEADDR 0 V), 0x32 (SLAVEADDR 3.3 V) and 0x34 (SLAVEADDR floating).

All registers are set to their default value when the supply voltage is below the UVLO threshold.

6.5.1.1 F/S-Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, see Figure 6-17. All I2C-compatible devices should recognize a start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse, see Figure 6-18. All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge, see Figure 6-19, by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that the communication link with a slave has been established.

The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data from the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high, see Figure 6-17. This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address

Attempting to read data from register addresses not listed in this section results in FFh being read out. FS I2C operation does not support repeated start

6.5.1.2 Diagrams of I2C Protocol

TPS650830 start_stp_lvsAU3.gif Figure 6-17 START and STOP Conditions
TPS650830 bit_trns_lvsAU3.gif Figure 6-18 Bit Transfer on the I2C-bus
TPS650830 if_ackn_lvsAU3.gif Figure 6-19 Acknowledge on the I2C-Bus
TPS650830 if_protocol_lvsAU3.gif Figure 6-20 Bus Protocol
TPS650830 if_write_lvsAU3.gif Figure 6-21 I2C Interface WRITE to Device in F/S Mode
TPS650830 if_read_lvsAU3.gif Figure 6-22 I2C Interface READ from Device in F/S Mode

6.6 Register Map

Table 6-3 Register Summary

Register Address Register Name Domain Short Description
x00 VENDORID UVLO Code that indicated a Texas Instruments' PMIC device.
x01 REVID UVLO Code to identify device revision and programming revision.
x02 IRQLVL1 RTC Top level interrupts
x04 PWRSRCINT RTC Input power interrupts
x05 PMUINT RTC PMU interrupts
x08 RESETIRQ1 RTC Emergency Shutdown interrupts
x09 RESETIRQ2 RTC Emergency Shutdown interrupts
x0B MPMUINT RTC Mask PMU interrupts
x0C MPWRSRCNT RTC Mask input power interrupts
x11 RESETIRQ1MASK RTC Mask Emergency Shutdown interrupts
x12 RESETIRQ2MASK RTC Mask Emergency Shutdown interrupts
x13 IRQLVL1MSK RTC Mask top level interrupt
x14 PBCONFIG RTC Power Button configuration
x15 PBSTATUS RTC Power Button Status
x16 PWRSTAT1 RTC VR Fault Reporting
x17 PWRSTAT2 RTC VR Fault Reporting
x18 PGMASK1 RTC Mask VR PGs from System Power Good Tree
x19 PGMASK2 RTC Mask VR PGs from System Power Good Tree
x30 VCCIOCNT UVLO VCCIO (PGD ) Control
x31 V5ADS3CNT UVLO V5A_DS3 (VR5 ) Control
x32 V33ADSWCNT UVLO V3.3A_DSW (VR3 ) Control
x33 V33APCHCNT UVLO V3.3A_PCH (PGE) Control
x34 V18ACNT UVLO V1.8A (VR2 ) Control
x35 V18U25UCNT UVLO V1.8U_2.5U (PGB) Control
x36 V1P2UCNT UVLO V1.2U / VDDQ (VR4) Control
x37 V100ACNT UVLO V1.00A (VR1) Control
x38 V08ACNT UVLO V0.85A (VR1 ) Control
x3B VRMODECTRL UVLO Force Low Power Mode
x3C DISCHCNT1 UVLO Discharge Resistors Settings
x3D DISCHCNT2 UVLO Discharge Resistors Settings
x3E DISCHCNT3 UVLO Discharge Resistors Settings
x3F DISCHCNT4 UVLO Discharge Resistors Settings
x40 PWRGDCNT1 UVLO System Level Power Goods
x41 VREN UVLO Deep Sleep Enable
x42 REGLOCK UVLO Lock for Control Registers, x30 - x38
x43 VRENPINMASK UVLO Mask hardware enable pins
x48 RSTCTRL RTC Reset Control
x49 SDWNCTRL UVLO Software Force Shutdown
x51 VDLMTCRT UVLO VDCSNS Settings
x69 ACOKDBDM UVLO ACOK Settings
x6A LOWBATTDET UVLO Battery Detection Settings
x6F SPWRSRCINT UVLO Input power Statuses
xD0 CLKCTRL1 RTC Clock Control
xDD COMPA_REF UVLO Comparator A Settings
xDE COMPB_REF UVLO Comparator B Settings
xDF COMPC_REF UVLO Comparator C Settings
xE0 COMPD_REF UVLO Comparator D Settings
xE1 COMPE_REF UVLO Comparator E Settings
xE2 COMPF_REF UVLO Comparator F Settings
xE3 COMPG_REF UVLO Comparator G Settings
xE4 COMPH_REF UVLO Comparator H Settings
xE5 PWRFAULT_MASK1 UVLO Mask VR Faults from Emergency Shutdown
xE6 PWRFAULT_MASK2 UVLO Mask VR Faults from Emergency Shutdown
xE7 PGOOD_STAT1 UVLO VR PGs Statuses
xE8 PGOOD_STAT2 UVLO VR PGs Statuses
xE9 MISC_BITS UVLO Misc. Bits
xEA STDY_CTRL RTC VCOMP and Standby Control
xEB TEMPCRIT RTC VR Critical Temperature
xEC TEMPHOT RTC VR Hot Temperature
xED OVERCURRENT RTC VR Overcurrent
xEE VREN_PIN_OVR UVLO VR Enable Override with Software

6.6.1 Registers

6.6.1.1 VENDORID Register (address = 0x00) [reset = 00100010]

Figure 6-23 VENDORID Register Format
B7 B6 B5 B4 B3 B2 B1 B0
VENDORID[7] VENDORID[6] VENDORID[5] VENDORID[4] VENDORID[3] VENDORID[2] VENDORID[1] VENDORID[0]
0 0 1 0 0 0 1 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-4 VENDORID Register Field Descriptions

Bit Field Type Reset Description
7:0 VENDORID[7:0] RW 00100010 Vendor ID

6.6.1.2 REVID Register (address = 0x01) [reset = 00000000]

Figure 6-24 REVID Register Format
B7 B6 B5 B4 B3 B2 B1 B0
DNUM[3] DNUM[2] DNUM[1] DNUM[0] OTPREV[3] OTPREV[2] REVID[1] REVID[0]
0 0 0 1 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-5 REVID Register Field Descriptions

Bit Field Type Reset Description
7:4 DNUM[3:0] RW 0000 Major revision ID
1010: A
1011: B
1100: C
1101: D
1110: E
1111: F
3:2 OTPREV[1:0] RW 00 Minor revision ID
0000: 0
0001: 1
0010: 2
0011: 3
0100: 4
0101: 5
0110: 6
0111: 7
1:0 REVID[1:0] RW 00 Minor revision ID
0000: 0
0001: 1
0010: 2
0011: 3
0100: 4
0101: 5
0110: 6
0111: 7

6.6.1.3 IRQLVL1 Register (address = 0x02) [reset = 00000000]

Figure 6-25 IRQLVL1 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESET RESERVED2 PMU RESERVED1[1] RESERVED1[0] PWRSRC RESERVED PWRBTN
0 0 0 0 0 0 0 0
RW R RW R R RW R RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-6 IRQLVL1 Register Field Descriptions

Bit Field Type Reset Description
7 RESET R 0 RESET interrupt
0: Not asserted
1: Asserted
6 RESERVED2 R 0
5 PMU R 0 Power monitor interrupt
0: Not asserted
1: Asserted
4:3 RESERVED1[1:0] R 00
2 PWRSRC R 0 Power source interrupt
0: Not asserted
1: Asserted
1 RESERVED R 0
0 PWRBTN RW 0 Power button interrupt
0: Not asserted
1: Asserted, write '1' to clear

6.6.1.4 PWRSRCINT Register (address = 0x04) [reset = 00000000]

Figure 6-26 PWRSRCINT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED1_PWRSRCINT LOWBATT2 LOWBATT1 ACOK PMICHOT RESERVED[2] RESERVED[1] RESERVED[0]
0 0 0 0 0 0 0 0
R RW RW RW RW R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-7 PWRSRCINT Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED1_PWRSRCINT R 0
6 LOWBATT2 RW 0 Low battery2 interrupt [rising-edge detect threshold = 1.25 V; falling-edge hysteresis = 125 mV]
0: No battery2 detected
1: Battery2 detected
5 LOWBATT1 RW 0 Low battery1 interrupt [rising-edge detect threshold =1.25 V; falling-edge hysteresis = 125 mV]
0: No battery1 detected
1: Battery1 detected
4 ACOK RW 0 AC/DC adapter detection interrupt. [rising-edge detect threshold =1.25 V; falling-edge hysteresis = 125 mV]
0: No adapter detected
1: Adapter detected
3 PMICHOT RW 0 PMIC internal temperature interrupt
0: PMIC temperature normal
1: PMIC temperature hot
2:0 RESERVED[2:0] R 000

6.6.1.5 PMUINT Register (address = 0x05) [reset = 00000000]

Figure 6-27 PMUINT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED2[2] RESERVED2[1] RESERVED2[0] PMUACOK RESERVED1_PMUINT PMUVDC RESERVED_PMUINT[1] RESERVED_PMUINT[0]
0 0 0 0 0 0 0 0
R R R RW R RW R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-8 PMUINT Register Field Descriptions

Bit Field Type Reset Description
7:5 RESERVED2[2:0] R 000
4 PMUACOK RW 0 Adapter detection interrupt
0: No Interrupt Pending
1: AC Adapter removed (SACOK H -> L)
3 RESERVED1_PMUINT R 0
2 PMUVDC RW 0 Power monitor critical supply voltage interrupt
0: Critical supply voltage over threshold limit
1: Critical supply voltage below threshold limit
1:0 RESERVED_PMUINT[1:0] R 00

6.6.1.6 RESETIRQ1 Register (address = 0x08) [reset = 00000000]

Figure 6-28 RESETIRQ1 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED1_RESETIRQ1[1] RESERVED1_RESETIRQ1[0] FCO VRFAULT RESERVED[3] RESERVED[2] RESERVED[1] RESERVED[0]
0 0 0 0 0 0 0 0
R R RW RW R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-9 RESETIRQ1 Register Field Descriptions

Bit Field Type Reset Description
7:6 RESERVED1_RESETIRQ1[1:0] R 00
5 FCO RW 0 Power button triggered reset interrupt
0: Power button counter has not forced an emergency reset
1: Power button counter has forced an emergency reset
4 VRFAULT RW 0 Voltage regulator triggered reset interrupt
0: Voltage regulator fault has not triggered an emergency reset
1: Voltage regulator fault has triggered an emergency reset
3:0 RESERVED[3:0] R 0000

6.6.1.7 RESETIRQ2 Register (address = 0x09) [reset = 00000000]

Figure 6-29 RESETIRQ2 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED1[5] RESERVED1[4] RESERVED1[3] RESERVED1[2] RESERVED1[1] RESERVED1[0] CRITTEMP RESERVED_RESETIRQ2
0 0 0 0 0 0 0 0
R R R R R R RW R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-10 RESETIRQ2 Register Field Descriptions

Bit Field Type Reset Description
7:2 RESERVED1[5:0] R 000000
1 CRITTEMP RW 0 Temperature triggered reset interrupt
0: Critical temperature not reached
1: Critical temperature reached, forcing emergency shutdown
0 RESERVED_RESETIRQ2 R 0

6.6.1.8 MPMUINT Register (address = 0x0B) [reset = 00010100]

Figure 6-30 MPMUINT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED2_MPMUINT[2] RESERVED2_MPMUINT[1] RESERVED2_MPMUINT[0] MPMUACOK RESERVED1_MPMUINT MPMUVDC RESERVED_MPMUINT[1] RESERVED_MPMUINT[0]
0 0 0 1 0 1 0 0
R R R RW R RW R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-11 MPMUINT Register Field Descriptions

Bit Field Type Reset Description
7:5 RESERVED2_MPMUINT[2:0] R 000
4 MPMUACOK RW 1 Power monitor critical supply voltage (adapter) mask interrupt
0: Not masked
1: Masked
3 RESERVED1_MPMUINT R 0
2 MPMUVDC RW 1 Power monitor critical supply voltage mask interrupt
0: Not masked
1: Masked
1:0 RESERVED_MPMUINT[1:0] R 00

6.6.1.9 MPWRSRCINT Register (address = 0x0C) [reset = 01111000]

Figure 6-31 MPWRSRCINT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED1_MPWRSRCINT MLOWBAT2 MLOWBAT1 MACOK MPMICHOT RESERVED_MPWRSRCINT[2] RESERVED_MPWRSRCINT[1] RESERVED_MPWRSRCINT[0]
0 1 1 1 1 0 0 0
R RW RW RW RW R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-12 MPWRSRCINT Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED1_MPWRSRCINT R 0
6 MLOWBAT2 RW 1 Low battery voltage mask interrupt
0: Not masked
1: Masked
5 MLOWBAT1 RW 1 Low battery voltage mask interrupt
0: Not masked
1: Masked
4 MACOK RW 1 AC/DC adapter detection mask interrupt
0: Not masked
1: Masked
3 MPMICHOT RW 1 PMIC internal temperature mask interrupt
0: Not masked
1: Masked
2:0 RESERVED_MPWRSRCINT[2:0] R 000

6.6.1.10 RESETIRQ1MASK Register (address = 0x11) [reset = 00110000]

Figure 6-32 RESETIRQ1MASK Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED1_RESETIRQ1MASK[1] RESERVED1_RESETIRQ1MASK[0] MFCO MVRFAULT RESERVED_RESETIRQ1MASK[3] RESERVED_RESETIRQ1MASK[2] RESERVED_RESETIRQ1MASK[1] RESERVED_RESETIRQ1MASK[0]
0 0 1 1 0 0 0 0
R R RW RW R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-13 RESETIRQ1MASK Register Field Descriptions

Bit Field Type Reset Description
7:6 RESERVED1_RESETIRQ1MASK[1:0] R 00
5 MFCO RW 1 Power button triggered reset mask interrupt
0: Not masked
1: Masked
4 MVRFAULT RW 1 Voltage regulator triggered reset mask interrupt
0: Not masked
1: Masked
3:0 RESERVED_RESETIRQ1MASK[3:0] R 0000

6.6.1.11 RESETIRQ2MASK Register (address = 0x12) [reset = 00000010]

Figure 6-33 RESETIRQ2MASK Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED1_RESETIRQ2MASK[5] RESERVED1_RESETIRQ2MASK[4] RESERVED1_RESETIRQ2MASK[3] RESERVED1_RESETIRQ2MASK[2] RESERVED1_RESETIRQ2MASK[1] RESERVED1_RESETIRQ2MASK[0] MCRITTEMP RESERVED_RESETIRQ2MASK
0 0 0 0 0 0 1 0
R R R R R R RW R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-14 RESETIRQ2MASK Register Field Descriptions

Bit Field Type Reset Description
7:2 RESERVED1_RESETIRQ2MASK[5:0] R 000000
1 MCRITTEMP RW 1 Temperature triggered reset mask interrupt
0: Not masked
1: Masked
0 RESERVED_RESETIRQ2 MASK R 0

6.6.1.12 IRQLVL1msK Register (address = 0x13) [reset = 10100101]

Figure 6-34 IRQLVL1msK Register Format
B7 B6 B5 B4 B3 B2 B1 B0
MRESET RESERVED2_IRQLVL1msK MPMU RESERVED1_IRQLVL1msK[1] RESERVED1_IRQLVL1msK[0] MPWRSRC RESERVED_IRQLVL1msK MPWRBTN
1 0 1 0 0 1 0 1
RW R RW R R RW R RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-15 IRQLVL1msK Register Field Descriptions

Bit Field Type Reset Description
7 MRESET RW 1 RESET mask interrupt
0: Not masked
1: Masked
6 RESERVED2_IRQLVL1msK R 0
5 MPMU RW 1 Power monitor mask interrupt
0: Not masked
1: Masked
4:3 RESERVED1_IRQLVL1msK[1:0] R 00
2 MPWRSRC RW 1 Power source mask interrupt
0: Not masked
1: Masked
1 RESERVED_IRQLVL1msK R 0
0 MPWRBTN RW 1 Power button mask interrupt
0: Not masked
1: Masked

6.6.1.13 PBCONFIG Register (address = 0x14) [reset = 00011111]

Figure 6-35 PBCONFIG Register Format
B7 B6 B5 B4 B3 B2 B1 B0
PWRBTNDBN CLRHT FLT[5] FLT[4] FLT[3] FLT[2] FLT[1] FLT[0]
0 0 0 1 1 1 1 1
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-16 PBCONFIG Register Field Descriptions

Bit Field Type Reset Description
7 PWRBTNDBN RW 0 Power button debounce
0: 30 ms
1: 0 ms (no debounce)
6 CLRHT RW 0 Reset of power button timer logic
0: No action
1: Reset of HT, bit is self clearing
5:0 FLT[5:0] RW 011111 Time that the button must be held to force an emergency reset
000000: 0 s
000001: 1 s
000010: 2 s
000011: 3 s
000100: 4 s
000101: 5 s
000110: 6 s
000111: 7 s
001000: 8 s
001001: 9 s
001010: 10 s
..
011111: 31 s
...
111100: 60 s
111101: 61 s
111110: 62 s
111111: 63 s

6.6.1.14 PBSTATUS Register (address = 0x15) [reset = 00000000]

Figure 6-36 PBSTATUS Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_PBSTATUS LVL HT[5] HT[4] HT[3] HT[2] HT[1] HT[0]
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-17 PBSTATUS Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED_PBSTATUS R 0
6 LVL R 0 Power button present level
0: Power button held
1: Power button released
5:0 HT[5:0] R 000000 Time that the button has been held
00000: Disabled
00001: Disabled
000010: 2 s
000011: 3 s
000100: 4 s
000101: 5 s
000110: 6 s
000111: 7 s
001000: 8 s
001001: 9 s
001010: 10 s
..
...
111100: 60 s
111101: 61 s
111110: 62 s
111111: 63 s

6.6.1.15 PWRSTAT1 Register (address = 0x16) [reset = 00000000]

Figure 6-37 PWRSTAT1 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
VCCIO_FAULT V5A_DS3_FAULT V33A_DSW_FAULT V33A_PCH_FAULT V18A_FAULT V18U_25U_FAULT V12U_FAULT V06DX_FAULT
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-18 PWRSTAT1 Register Field Descriptions

Bit Field Type Reset Description
7 VCCIO_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault
6 V5A_DS3_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault
5 V33A_DSW_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault
4 V33A_PCH_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault
3 V18A_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault
2 V18U_25U_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault
1 V12U_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault
0 V06DX_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault

6.6.1.16 PWRSTAT2 Register (address = 0x17) [reset = 00000000]

Figure 6-38 PWRSTAT2 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED[5] RESERVED[4] RESERVED[3] RESERVED[2] RESERVED[1] RESERVED[0] V100A_FAULT V085A_FAULT
0 0 0 0 0 0 0 0
R R R R R R RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-19 PWRSTAT2 Register Field Descriptions

Bit Field Type Reset Description
7:2 RESERVED[5:0] R 000000
1 V100A_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault
0 V085A_FAULT RW 0 These bits indicate that the VR has lost regulation
0: Clears register
1: Indicates power fault

6.6.1.17 PGMASK1 Register (address = 0x18) [reset = 00000000]

Figure 6-39 PGMASK1 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
MVCCIOPG MV085APG MV100APG MV18APG MV33APCHPG MV5ADS3PG MV33ADSWPG MV100SPG
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-20 PGMASK1 Register Field Descriptions

Bit Field Type Reset Description
7 MVCCIOPG RW 0 VCCIO PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
6 MV085APG RW 0 V0.85A PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
5 MV100APG RW 0 V100A PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
4 MV18APG RW 0 V1.8A PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
3 MV33APCHPG RW 0 V3.3A PCH PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
2 MV5ADS3PG RW 0 V5A DS3 PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
1 MV33ADSWPG RW 0 V3.3A DSW PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
0 MV100SPG RW 0 V100S PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)

6.6.1.18 PGMASK2 Register (address = 0x19) [reset = 00000000]

Figure 6-40 PGMASK2 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_PGMASK2[3] RESERVED_PGMASK2[2] RESERVED_PGMASK2[1] RESERVED_PGMASK2[0] V18U25UPG MV12UPG MV33SPG MV18SPG
0 0 0 0 0 0 0 0
R R R R RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-21 PGMASK2 Register Field Descriptions

Bit Field Type Reset Description
7:4 RESERVED_PGMASK2[3:0] R 0000
3 V18U25UPG RW 0 V1.8_2.5U PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
2 MV12UPG RW 0 V1.2U PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
1 MV33SPG RW 0 V3.3S PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)
0 MV18SPG RW 0 V1.8S PG is part of the power good tree
0: Power Good function is enabled
1: Power Good function is masked and set to 1 (not part of the Power Good tree)

6.6.1.19 VCCIOCNT Register (address = 0x30) [reset = 00001010]

Figure 6-41 VCCIOCNT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_VCCIOCNT CSDECAYEN VCCIOVSEL[1] VCCIOVSEL[0] AOACCNTVCCIO[1] AOACCNTVCCIO[0] CTLVVCCIO[1] CTLVVCCIO[0]
0 0 0 0 1 0 1 0
R RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-22 VCCIOCNT Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED_VCCIOCNT R 0
6 CSDECAYEN RW 0 Enables VCCIO decay when SLP_S0# is asserted. [wait 2us after removing FPWM, before entering DECAY mode. Direct FPWM to DECAY by SLP0Z may cause ringing. Decay exit time within 100us not guaranteed for Vout > 1V.]
0: VCCIO stays at voltage set by VCCIOVSEL independent of state of SLP_S0#
1: VCCIO decays to 0V, PGOOD is maintained when SLP_S0# is asserted (low)
5:4 VCCIOVSEL[1:0] RW 00 Output voltage select
00: 0.975V
01: 0.950V
10: 0.875V
11: 0.850V
3:2 AOACCNTVCCIO[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) - changes bits D[1:0] on exit
00: No change in bits D[1:0] - fast change mode disabled
01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM)
10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM)
11: Bits D[1:0] set to 11, forced PWM operation
1:0 CTLVVCCIO[1:0] RW 10 Mode control (V4)
00: Converter disabled
01: Auto Mode, (automatic transition from PFM to PWM)
10: Auto Mode, (automatic transition from PFM to PWM)
11: Forced PWM operation

6.6.1.20 V5ADS3CNT Register (address = 0x31) [reset = 00101010]

Figure 6-42 V5ADS3CNT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V5ADS3LVSEL[1] V5ADS3LVSEL[0] V5ADS3VSEL[1] V5ADS3VSEL[0] AOACCNTV5ADS3[1] AOACCNTV5ADS3[0] CTLV5ADS3[1] CTLV5ADS3[0]
0 0 1 0 1 0 1 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-23 V5ADS3CNT Register Field Descriptions

Bit Field Type Reset Description
7:6 V5ADS3LVSEL[1:0] RW 00 V5ADS3 low power mode output voltage set point - set at assertion of SLP_S0#
00: Disabled, voltage stays at value set by V5ADS3VSEL[1:0]
01: Vnom - 4%
10: Vnom - 3%
11: Vnom - 2%
5:4 V5ADS3VSEL[1:0] RW 10 Output voltage select
00: Vnom + 3%
01: Vnom + 2%
10: Vnom
11: Vnom - 2%
3:2 AOACCNTV5ADS3[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) - changes bits D[1:0] on exit
00: No change in bits D[1:0] - fast change mode disabled
01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM)
10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM)
11: Bits D[1:0] set to 11, forced PWM operation
1:0 CTLV5ADS3[1:0] RW 10 Mode control (V5)
00: Converter disabled
01: Auto Mode, (automatic transition from PFM to PWM)
10: Auto Mode, (automatic transition from PFM to PWM)
11: Forced PWM operation

6.6.1.21 V33ADSWCNT Register (address = 0x32) [reset = 00101010]

Figure 6-43 V33ADSWCNT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V33ADSWLVSEL[1] V33ADSWLVSEL[0] V33ADSWVSEL[1] V33ADSWVSEL[0] AOACCNTV33ADSW[1] AOACCNTV33ADSW[0] CTLV33ADSW[1] CTLV33ADSW[0]
0 0 1 0 1 0 1 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-24 V33ADSWCNT Register Field Descriptions

Bit Field Type Reset Description
7:6 V33ADSWLVSEL[1:0] RW 00 V33A_DSW low power mode output voltage set point - set at assertion of SLP_S0#
00: Disabled, voltage stays at value set by V33ADSWVSEL[1:0]
01: Vnom - 4%
10: Vnom - 3%
11: Vnom - 2%
5:4 V33ADSWVSEL[1:0] RW 10 Output voltage select
00: Vnom + 3%
01: Vnom + 2%
10: Vnom
11: Vnom - 2%
3:2 AOACCNTV33ADSW[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) - changes bits D[1:0] on exit
00: No change in bits D[1:0] - fast change mode disabled
01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM)
10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM)
11: Bits D[1:0] set to 11, forced PWM operation
1:0 CTLV33ADSW[1:0] RW 10 Mode control (V6)
00: Converter disabled
01: Auto Mode, (automatic transition from PFM to PWM)
10: Auto Mode, (automatic transition from PFM to PWM)
11: Forced PWM operation

6.6.1.22 V33APCHCNT Register (address = 0x33) [reset = 00001010]

Figure 6-44 V33APCHCNT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_V33APCHCNT[3] RESERVED_V33APCHCNT[2] RESERVED_V33APCHCNT[1] RESERVED_V33APCHCNT[0] AOACCNTV33APCH[1] AOACCNTV33APCH[0] CTLV33APCH[1] CTLV33APCH[0]
0 0 0 0 1 0 1 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-25 V33APCHCNT Register Field Descriptions

Bit Field Type Reset Description
7:4 RESERVED_V33APCHCNT[3:0] RW 0000
3:2 AOACCNTV33APCH[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) - changes bits D[1:0] on exit
00: No change in bits D[1:0] - fast change mode disabled
01: Bits D[1:0] set to 01
10: Bits D[1:0] set to 10
11: Bits D[1:0] set to 11
1:0 CTLV33APCH[1:0] RW 10 Mode control (V7)
00: Disabled
01: Enabled
10: Enabled
11: Enabled

6.6.1.23 V18ACNT Register (address = 0x34) [reset = 00101010]

Figure 6-45 V18ACNT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V18ALVSEL[1] V18ALVSEL[0] V18AVSEL[1] V18AVSEL[0] AOACCNTV18A[1] AOACCNTV18A[0] CTLV18A[1] CTLV18A[0]
0 0 1 0 1 0 1 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-26 V18ACNT Register Field Descriptions

Bit Field Type Reset Description
7:6 V18ALVSEL[1:0] RW 00 V18A low power mode output voltage set point - set at assertion of SLP_S0#
00: Disabled, voltage stays at value set by V18AVSEL[1:0]
01: Vnom - 4%
10: Vnom - 3%
11: Vnom - 2%
5:4 V18AVSEL[1:0] RW 10 Output voltage select
00: Vnom + 3%
01: Vnom + 2%
10: Vnom
11: Vnom - 2%
3:2 AOACCNTV18A[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) - changes bits D[1:0] on exit
00: No change in bits D[1:0] - fast change mode disabled
01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM)
10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM)
11: Bits D[1:0] set to 11, forced PWM operation
1:0 CTLV18A[1:0] RW 10 Mode control (V8)
00: Converter disabled
01: Auto Mode, (automatic transition from PFM to PWM)
10: Auto Mode, (automatic transition from PFM to PWM)
11: Forced PWM operation

6.6.1.24 V18U25UCNT Register (address = 0x35) [reset = 00001010]

Figure 6-46 V18U25UCNT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_V18U25UCNT[3] RESERVED_V18U25UCNT[2] RESERVED_V18U25UCNT[1] RESERVED_V18U25UCNT[0] AOACCNTV18U25U[1] AOACCNTV18U25U[0] CTLV18U25U[1] CTLV18U25U[0]
0 0 0 0 1 0 1 0
R R R R RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-27 V18U25UCNT Register Field Descriptions

Bit Field Type Reset Description
7:4 RESERVED_V18U25UCNT[3:0] R 0000
3:2 AOACCNTV18U25U[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) - changes bits D[1:0] on exit
00: No change in bits D[1:0] - fast change mode disabled
01: Bits D[1:0] set to 01
10: Bits D[1:0] set to 10
11: Bits D[1:0] set to 11
1:0 CTLV18U25U[1:0] RW 10 Mode control (V9)
00: Disabled
01: Enabled
10: Enabled
11: Enabled

6.6.1.25 V1P2UCNT Register (address = 0x36) [reset = 00111010]

Figure 6-47 V1P2UCNT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V1P2ULVSEL V1P2UVSEL[2] V1P2UVSEL[1] V1P2UVSEL[0] AOACCNTV1P2U[1] AOACCNTV1P2U[0] CTLV1P2U[1] CTLV1P2U[0]
0 0 1 1 1 0 1 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-28 V1P2UCNT Register Field Descriptions

Bit Field Type Reset Description
7 V1P2ULVSEL RW 0 V1.2U low power mode output voltage set point - set at assertion of SLP_S0#
0: Disabled, voltage stays at value set by V1P2UVSEL
1: Vnom - 3%
6:4 V1P2UVSEL[2:0] RW 011 Output voltage select
000: Vnom + 3%
001: Vnom + 2%
010: Vnom + 1%
011: Vnom + 0%
100: Vnom - 1%
101: Vnom - 2%
110: Vnom - 3%
111: Vnom -4%
3:2 AOACCNTV1P2U[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) - changes bits D[1:0] on exit
00: no change in bits D[1:0] - fast change mode disabled
01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM)
10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM)
11: Bits D[1:0] set to 11, forced PWM operation
1:0 CTLV1P2U[1:0] RW 10 Mode control (V10)
00: Converter disabled
01: Auto Mode, (automatic transition from PFM to PWM)
10: Auto Mode, (automatic transition from PFM to PWM)
11: Forced PWM operation

6.6.1.26 V100ACNT Register (address = 0x37) [reset = 00011010]

Figure 6-48 V100ACNT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V100ALVSEL[1] V100ALVSEL[0] V100AVSEL[1] V100AVSEL[0] AOACCNTV100A[1] AOACCNTV100A[0] CTLV100A[1] CTLV100A[0]
0 0 0 1 1 0 1 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-29 V100ACNT Register Field Descriptions

Bit Field Type Reset Description
7:6 V100ALVSEL[1:0] RW 00 V100A low power mode output voltage set point - set at assertion of SLP_S0#
00: Disabled, voltage stays at value set by V100AVSEL[1:0]
01: Vnom - 4%
10: Vnom - 3%
11: Vnom - 2%
5:4 V100AVSEL[1:0] RW 01 Output voltage select
00: Vnom + 5% (1.05 V)
01: Vnom (1 V)
10: Vnom - 2.5% (0.975 V)
11: Vnom - 5% (0.95V)
3:2 AOACCNTV100A[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) - changes bits D[1:0] on exit
00: No change in bits D[1:0] - fast change mode disabled
01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM)
10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM)
11: Bits D[1:0] set to 11, forced PWM operation
1:0 CTLV100A[1:0] RW 10 Mode control (V11)
00: Converter disabled
01: Auto Mode, (automatic transition from PFM to PWM)
10: Auto Mode, (automatic transition from PFM to PWM)
11: Forced PWM operation

6.6.1.27 V085ACNT Register (address = 0x38) [reset = 00101010]

Figure 6-49 V085ACNT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V085ALVSEL[1] V085ALVSEL[0] V085AVSEL[1] V085AVSEL[0] AOACCNTV085A[1] AOACCNTV085A[0] CTLV085A[1] CTLV085A[0]
0 0 1 0 1 0 1 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-30 V085ACNT Register Field Descriptions

Bit Field Type Reset Description
7:6 V085ALVSEL[1:0] RW 00 V085A low power mode output voltage set point - set at assertion of SLP_S0#
00: Disabled, voltage stays at value set by V085AVSEL[1:0]
01: 0.70 V
10: 0.75 V
11: 0.80 V
5:4 V085AVSEL[1:0] RW 00 Output voltage select
00: 0.95 V
01: 0.90 V
10: 0.85 V
11: 0.80 V
3:2 AOACCNTV085A[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) - changes bits D[1:0] on exit
00: No change in bits D[1:0] - fast change mode disabled
01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM)
10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM)
11: Bits D[1:0] set to 11, forced PWM operation
1:0 CTLV085A[1:0] RW 10 Mode control (V12)
00: Converter disabled
01: Auto Mode, (automatic transition from PFM to PWM)
10: Auto Mode, (automatic transition from PFM to PWM)
11: Forced PWM operation

6.6.1.28 VRMODECTRL Register (address = 0x3B) [reset = 00111111]

Figure 6-50 VRMODECTRL Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_VRMODECTRL[1] RESERVED_VRMODECTRL[0] V33ADSW_LPM VCCIO_LPM V085A_LPM V12U_LPM V100A_LPM V5ADS3_LPM
0 0 1 1 1 1 1 1
R R RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-31 VRMODECTRL Register Field Descriptions

Bit Field Type Reset Description
7:6 RESERVED_VRMODECTRL[1:0] R 00
5 V33ADSW_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV33ADSW [1:0] bits of V33ADSWCNT register.
0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V33ADSWCNT, bits CTLV33ADSW [1:0] when STANDBY# is low}
1: Mode set by CTLV33ADSW [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV33ADSW [1:0] when STANDBY# is low}
4 VCCIO_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLVCCIO [1:0] bits of VCCIOCNT register.
0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register VCCIOCNT, bits CTLVCCIO [1:0] when STANDBY# is low}
1: Mode set by CTLVCCIO [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLVCCIO [1:0] when STANDBY# is low}
3 V085A_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV085A [1:0] register.
0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V085ACNT, bits CTLV085A [1:0] when STANDBY# is low}
1: Mode set by CTLV085A [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV085A [1:0] when STANDBY# is low}
2 V12U_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV12U [1:0] bits in V12UCNT register.
0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V12UCNT, bits CTLV12U [1:0] when STANDBY# is low}
1: Mode set by CTLV12U [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV12U [1:0] when STANDBY# is low}
1 V100A_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV100A [1:0] bits in V100ACNTregister.
0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V100ACNT, bits CTLV100A [1:0] when STANDBY# is low}
1: Mode set by CTLV100A [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV100A[1:0] when STANDBY# is low}
0 V5ADS3_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV5ADS3 [1:0] bits in V5ADS3CNT register.
0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V5ADS3,CNT bits CTLVV33ADSW [1:0] when STANDBY# is low}
1: Mode set by CTLV5ADS3 [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV5ADS3 [1:0] when STANDBY# is low}

6.6.1.29 DISCHCNT1 Register (address = 0x3C) [reset = 00000000]

Figure 6-51 DISCHCNT1 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_DISCHCNT1[5] RESERVED_DISCHCNT1[4] RESERVED_DISCHCNT1[3] RESERVED_DISCHCNT1[2] RESERVED_DISCHCNT1[1] RESERVED_DISCHCNT1[0] VCCIODISCHG[1] VCCIODISCHG[0]
0 0 0 0 0 0 0 0
R R R R R R RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-32 DISCHCNT1 Register Field Descriptions

Bit Field Type Reset Description
7:2 RESERVED_DISCHCNT1[5:0] R 000000
1:0 VCCIODISCHG[1:0] RW 00 VCCIO discharge resistance at VSD, (TPS650831 at FBVR3P)
00: >1000 kΩ
01: 125 Ω
10: 225 Ω
11: 550 Ω

6.6.1.30 DISCHCNT2 Register (address = 0x3D) [reset = 00000000]

Figure 6-52 DISCHCNT2 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V5ADS3DISCHG[1] V5ADS3DISCHG[0] V33ADSWDISCHG[1] V33ADSWDISCHG[0] V33PCHDISCHG[1] V33PCHDISCHG[0] V18ADISCH[1] V18ADISCH[0]
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-33 DISCHCNT2 Register Field Descriptions

Bit Field Type Reset Description
7:6 V5ADS3DISCHG[1:0] RW 00 V5ADS3 discharge resistance at FBVR5P, (TPS650831 at VSC)
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
5:4 V33ADSWDISCHG[1:0] RW 00 V33A_DSW discharge resistance at FBVR3P, (TPS650831 at VSD)
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
3:2 V33PCHDISCHG[1:0] RW 00 V33A_PCH discharge resistance at VSA
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
1:0 V18ADISCH[1:0] RW 00 V18A discharge resistance at FBVR2P, (TPS650831 at FBVR5P)
00: 860 Ω
01: 100 Ω
10: 200 Ω
11: 500 Ω

6.6.1.31 DISCHCNT3 Register (address = 0x3E) [reset = 00000000]

Figure 6-53 DISCHCNT3 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V18U25UDISCHG[1] V18U25UDISCHG[0] V12UDISCHG[1] V12UDISCHG[0] V100ADISCHG[1] V100ADISCHG[0] V085ADISCH[1] V085ADISCH[0]
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-34 DISCHCNT3 Register Field Descriptions

Bit Field Type Reset Description
7:6 V18U25UDISCHG[1:0] RW 00 V1.8U_2.5U discharge resistance at VSB
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
5:4 V12UDISCHG[1:0] RW 00 V1.2U discharge resistance at FBVR4P
00: >1000 kΩ
01: 125 Ω
10: 225 Ω
11: 550 Ω
3:2 V100ADISCHG[1:0] RW 00 V100A discharge resistance at FBVR1P
00: >1000 kΩ
01: 125 Ω
10: 225 Ω
11: 550 Ω
1:0 V085ADISCH[1:0] RW 00 V085A discharge resistance, (TPS650831 at FBVR2P)
00: >1000 kΩ
01: 150 Ω
10: 250 Ω
11: 575 Ω

6.6.1.32 DISCHCNT4 Register (address = 0x3F) [reset = 00000000]

Figure 6-54 DISCHCNT4 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_DISCHCNT4[1] RESERVED_DISCHCNT4[0] V33SDISCHG[1] V33SDISCHG[0] V18SDISCHG[1] V18SDISCHG[0] V100SDISCH[1] V100SDISCH[0]
0 0 0 0 0 0 0 0
R R RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-35 DISCHCNT4 Register Field Descriptions

Bit Field Type Reset Description
7:6 RESERVED_DISCHCNT4[1:0] R 00
5:4 V33SDISCHG[1:0] RW 00 V3.3S discharge resistance at VSE
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
3:2 V18SDISCHG[1:0] RW 00 V18S discharge resistance at VSF
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
1:0 V100SDISCH[1:0] RW 00 V100S discharge resistance at VSG
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω

6.6.1.33 PWRGDCNT1 Register (address = 0x40) [reset = 01011111 ]

Figure 6-55 PWRGDCNT1 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_PWRGDCNT1 RSMRSTN_PWRGD[1] RSMRSTN_PWRGD[0] PCH_PWROK[1] PCH_PWROK[0] DEL_ALL_SYS_PWRGD[2] DEL_ALL_SYS_PWRGD[1] DEL_ALL_SYS_PWRGD[0]
0 1 0 1 1 1 1 1
R RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-36 PWRGDCNT1 Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED_PWRGDCNT1 R 0
6:5 RSMRSTN_PWRGD[1:0] RW 10 Delay of RSMRSTN_PWRGD, [RTC = 30.5 µs ±10%]
00: No Delay
01: 164x RTC (5.5 ms)
10: 360x RTC (11 ms)
11: 721x RTC (22 ms)
4:3 PCH_PWROK[1:0] RW 11 Delay of PCH_PWROK compared to ALL_SYS_PWRGD, [RTC = 30.5 µs ±10%]
00: 82x RTC (2.5 ms)
01: 164x RTC (5 ms)
10: 328x RTC (10 ms)
11: 656x RTC (20 ms)
2:0 DEL_ALL_SYS_PWRGD[2:0] RW 111 Delay of SYS_PWR_OK compared to ALL_SYS_PWRGD, [RTC = 30.5 µs ±10%]
000: 82x RTC (2.5 ms)
001: 164x RTC (5 ms)
010: 328x RTC (10 ms)
011: 492x RTC (15 ms)
100: 656x RTC (20 ms)
101: 1640x RTC (50 ms)
110: 2460x RTC (75 ms)
111: 3280x RTC (100 ms)

6.6.1.34 VREN Register (address = 0x41) [reset = 00000000]

Figure 6-56 VREN Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_VREN[5] RESERVED_VREN[4] RESERVED_VREN[3] RESERVED_VREN[2] RESERVED_VREN[1] RESERVED_VREN[0] EC_SLP_S4 EC_DS4
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-37 VREN Register Field Descriptions

Bit Field Type Reset Description
7:2 RESERVED_VREN[5:0] RW 000000
1 EC_SLP_S4 RW 0 0: Disable
1: Enable
0 EC_DS4 RW 0 0: Disable
1: Enable

6.6.1.35 REGLOCK Register (address = 0x42) [reset = 00000000]

Figure 6-57 REGLOCK Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED[6] RESERVED[5] RESERVED[4] RESERVED[3] RESERVED[2] RESERVED[1] RESERVED[0] CNTLOCK
0 0 0 0 0 0 0 0
R R R R R R R RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-38 REGLOCK Register Field Descriptions

Bit Field Type Reset Description
7:1 RESERVED[6:0] R 0000000
0 CNTLOCK RW 0 Locks all V*CNT registers
0: All V*CNT registers are unlocked and can be overwritten
1: All V*CNT registers are locked and cannot be overwritten

6.6.1.36 VRENPINMASK Register (address = 0x43) [reset = 00000000]

Figure 6-58 VRENPINMASK Register Format
B7 B6 B5 B4 B3 B2 B1 B0
MV12EN MV11EN MV10EN MV9EN MV8EN MV7EN MV5EN MV4EN
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-39 VRENPINMASK Register Field Descriptions

Bit Field Type Reset Description
7 MV12EN RW 0 V12 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
6 MV11EN RW 0 V11 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
5 MV10EN RW 0 V10 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
4 MV9EN RW 0 V9 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
3 MV8EN RW 0 V8 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
2 MV7EN RW 0 V7 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
1 MV5EN RW 0 V5 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
0 MV4EN RW 0 V4 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable

6.6.1.37 RSTCTRL Register (address = 0x48) [reset = 00011100]

Figure 6-59 RSTCTRL Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_RSTCTRL[2] RESERVED_RSTCTRL[1] RESERVED_RSTCTRL[0] TRST[1] TRST[0] VTHRST[2] VTHRST[1] VTHRST[0]
0 0 0 1 1 1 0 0
R R R RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-40 RSTCTRL Register Field Descriptions

Bit Field Type Reset Description
7:5 RESERVED_RSTCTRL[2:0] R 000
4:3 TRST[1:0] RW 11 Reset time duration
00: 20 ms
01: 40 ms
10: 80 ms
11: 200 ms
2:0 VTHRST[2:0] RW 100 Reset voltage threshold
000: 1.4 V
001: 1.5 V
010: 1.6 V
011: 1.7 V
100: 2.4 V
101: 2.6 V
110: 2.8 V
111: 3.0 V

6.6.1.38 SDWNCTRL Register (address = 0x49) [reset = 00000000]

Figure 6-60 SDWNCTRL Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_SDWNCTRL[6] RESERVED_SDWNCTRL[5] RESERVED_SDWNCTRL[4] RESERVED_SDWNCTRL[3] RESERVED_SDWNCTRL[2] RESERVED_SDWNCTRL[1] RESERVED_SDWNCTRL[0] SDWN
0 0 0 0 0 0 0 0
R R R R R R R RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-41 SDWNCTRL Register Field Descriptions

Bit Field Type Reset Description
7:1 RESERVED_SDWNCTRL[6:0] R 0000000
0 SDWN RW 0 Forced emergency reset, bit is self clearing
0: No action
1: Force emergency reset

6.6.1.39 VDLMTCRT Register (address = 0x51) [reset = 00000101]

Figure 6-61 VDLMTCRT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_VDLMTCRT VDLMTCOMP TDBNCVDLMTCRT[1] TDBNCVDLMTCRT[0] VDLMTCRTH[3] VDLMTCRTH[2] VDLMTCRTH[1] VDLMTCRTH[0]
0 0 0 0 0 1 0 1
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-42 VDLMTCRT Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED_VDLMTCRT RW 0
6 VDLMTCOMP RW 0 Critical supply voltage comparator for VDCSNS pin input voltage sense. Connect voltage divider resistors from VIN to detect when input voltage is low
0: disable
1: enable
5:4 TDBNCVDLMTCRT[1:0] RW 00 Supply voltage monitor debounce of VDCSNS input voltage sense pin
00: No Deglitch
01: 10 µs
10: 1x RTC (30us)
11: 2x RTC (60us)
3:0 VDLMTCRTH[3:0] RW 0101 Critical supply voltage falling threshold on VDCSNS pin. Connect voltage divider resistors from VIN to detect when input voltage is low. For 2S should be 4X top resistor, X bottom resistor. [rising hysteresis = 20 mV]
0000: no limit
0001: 1.2 V
0010: 1.18 V
0011: 1.16 V
0100: 1.14 V
0101: 1.12 V
0110: 1.10 V
0111: 1.08 V
1xxx: NA

6.6.1.40 ACOKDBDM Register (address = 0x69) [reset = 00001111]

Figure 6-62 ACOKDBDM Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_ACOKDBDM[3] RESERVED_ACOKDBDM[2] RESERVED_ACOKDBDM[1] RESERVED_ACOKDBDM[0] ACOKDB[1] ACOKDB[0] ACOKDM[1] ACOKDM[0]
0 0 0 0 1 1 1 1
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-43 ACOKDBDM Register Field Descriptions

Bit Field Type Reset Description
7:4 RESERVED_ACOKDBDM[3:0] RW 0000
3:2 ACOKDB[1:0] RW 11 Adapter detection debounce time
00: 81 µs
01: 10 ms
10: 20 ms
11: 30 ms
1:0 ACOKDM[1:0] RW 11 Adapter detection mode
00: reserved
01: low-to-high
10: high-to-low
11: both, low-to-high and high-to-low

6.6.1.41 LOWBATTDET Register (address = 0x6A) [reset = 11111000]

Figure 6-63 LOWBATTDET Register Format
B7 B6 B5 B4 B3 B2 B1 B0
LOWBATTDB[1] LOWBATTDB[0] LOWBATT2_EN LOWBATT1_EN ACIN_EN RESERVED_LOWBATTDET[2] RESERVED_LOWBATTDET[1] RESERVED_LOWBATTDET[0]
1 1 1 1 1 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-44 LOWBATTDET Register Field Descriptions

Bit Field Type Reset Description
7:6 LOWBATTDB[1:0] RW 11 Low battery detection debounce time
00: 4 RTC periods (120 µs)
01: 32 RTC periods (960 µs)
10: 64 RTC periods (1920 µs)
11: 128 RTC periods (3840 µs)
5 LOWBATT2_EN RW 1 Low battery Two detection Enable
0: Disable
1: Enable
4 LOWBATT1_EN RW 1 Low battery One detection Enable
0: Disable
1: Enable
3 ACIN_EN RW 1 AC IN Comparator
0: Disable
1: Enable
2:0 RESERVED_LOWBATTDET[2:0] RW 000

6.6.1.42 SPWRSRCINT Register (address = 0x6F) [reset = 00000000]

Figure 6-64 SPWRSRCINT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED1_SPWRSRCINT SLOWBATT2 SLOWBATT1 SACOK RESERVED_SPWRSRCINT[3] RESERVED_SPWRSRCINT[2] RESERVED_SPWRSRCINT[1] RESERVED_SPWRSRCINT[0]
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-45 SPWRSRCINT Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED1_SPWRSRCINT R 0
6 SLOWBATT2 R 0 LOWBATT2 detection status
0: BATT2 above threshold
1: BATT2 below threshold
5 SLOWBATT1 R 0 LOWBATT1 detection status
0: BATT1 above threshold
1: BATT1 below threshold
4 SACOK R 0 AC adapter (ACOK) detection status
0: Adapter removed
1: Adapter inserted
3:0 RESERVED_SPWRSRCINT[3:0] R 0000

6.6.1.43 CLKCTRL1 Register (address = 0xD0) [reset = 00000000]

Figure 6-65 CLKCTRL1 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_CLKCTRL1[6] RESERVED_CLKCTRL1[5] RESERVED_CLKCTRL1[4] RESERVED_CLKCTRL1[3] RESERVED_CLKCTRL1[2] RESERVED_CLKCTRL1[1] RESERVED_CLKCTRL1[0] ECWAKEEN
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-46 CLKCTRL1 Register Field Descriptions

Bit Field Type Reset Description
7:1 RESERVED_CLKCTRL1[6:0] RW 0000000
0 ECWAKEEN RW 0 1 Hz clock
0: clock OFF
1: Clock ON

6.6.1.44 COMPA_REF Register (address = 0xDD) [reset = 00000000]

Figure 6-66 COMPA_REF Register Format
B7 B6 B5 B4 B3 B2 B1 B0
COMPA_MODE COMPA_DVS[3] COMPA_DVS[2] COMPA_DVS[1] COMPA_DVS[0] COMPA_VSEL[2] COMPA_VSEL[1] COMPA_VSEL[0]
X X X X X X X X
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-47 COMPA_REF Register Field Descriptions

Bit Field Type Reset Description
7 COMPA_Mode RW 0 Comparator Mode:
0: PGOOD Mode
1: Comparator Mode
6:3 COMPA_DVS[3:0] RW 0000 Comparator Window Voltage Shifting:
% deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V
0000 = + 3% or 1.05 V
0001 = + 2% or 1 V
0010 = + 1% or 0.975 V
0011 = + 0% or 0.95 V
0100 = - 1% or 0.9 V
0101 = - 2% or 0.875 V
0110 = - 3% or 0.85 V
0111 = - 4% or 0.8 V
1000 = 0.75 V
1001 = 0.7 V
2:0 COMPA_VSEL[2:0] RW 000 Comparator Window Voltage Select:
000 = 1 V
001 = 1.2 V
010 = 1.5 V
011 = 1.8 V
100 = 1.1 V
101 = 1.35 V
110 = 3.3 V
111 = 2.5 V / 5 V

6.6.1.45 COMPB_REF Register (address = 0xDE) [reset = 00000000]

Figure 6-67 COMPB_REF Register Format
B7 B6 B5 B4 B3 B2 B1 B0
COMPB_MODE COMPB_DVS[3] COMPB_DVS[2] COMPB_DVS[1] COMPB_DVS[0] COMPB_VSEL[2] COMPB_VSEL[1] COMPB_VSEL[0]
X X X X X X X X
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-48 COMPB_REF Register Field Descriptions

Bit Field Type Reset Description
7 COMPB_Mode RW 0 Comparator Mode:
0: PGOOD Mode
1: Comparator Mode
6:3 COMPB_DVS[3:0] RW 0000 Comparator Window Voltage Shifting:
% deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V
0000 = + 3% or 1.05 V
0001 = + 2% or 1 V
0010 = + 1% or 0.975 V
0011 = + 0% or 0.95 V
0100 = - 1% or 0.9 V
0101 = - 2% or 0.875 V
0110 = - 3% or 0.85 V
0111 = - 4% or 0.8 V
1000 = 0.75 V
1001 = 0.7 V
2:0 COMPB_VSEL[2:0] RW 000 Comparator Window Voltage Select:
000 = 1 V
001 = 1.2 V
010 = 1.5 V
011 = 1.8 V
100 = 1.1 V
101 = 1.35 V
110 = 3.3 V
111 = 2.5 V / 5 V

6.6.1.46 COMPC_REF Register (address = 0xDF) [reset = 00000000]

Figure 6-68 COMPC_REF Register Format
B7 B6 B5 B4 B3 B2 B1 B0
COMPC_MODE COMPC_DVS[3] COMPC_DVS[2] COMPC_DVS[1] COMPC_DVS[0] COMPC_VSEL[2] COMPC_VSEL[1] COMPC_VSEL[0]
1 0 0 0 1 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-49 COMPC_REF Register Field Descriptions

Bit Field Type Reset Description
7 COMPC_Mode RW 0 Comparator Mode:
0: PGOOD Mode
1: Comparator Mode
6:3 COMPC_DVS[3:0] RW 0000 Comparator Window Voltage Shifting:
% deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V
0000 = + 3% or 1.05 V
0001 = + 2% or 1 V
0010 = + 1% or 0.975 V
0011 = + 0% or 0.95 V
0100 = - 1% or 0.9 V
0101 = - 2% or 0.875 V
0110 = - 3% or 0.85 V
0111 = - 4% or 0.8 V
1000 = 0.75 V
1001 = 0.7 V
2:0 COMPC_VSEL[2:0] RW 000 Comparator Window Voltage Select:
000 = 1 V
001 = 1.2 V
010 = 1.5 V
011 = 1.8 V
100 = 1.1 V
101 = 1.35 V
110 = 3.3 V
111 = 2.5 V / 5 V

6.6.1.47 COMPD_REF Register (address = 0xE0) [reset = 00000000]

Figure 6-69 COMPD_REF Register Format
B7 B6 B5 B4 B3 B2 B1 B0
COMPD_MODE COMPD_DVS[3] COMPD_DVS[2] COMPD_DVS[1] COMPD_DVS[0] COMPD_VSEL[2] COMPD_VSEL[1] COMPD_VSEL[0]
X X X X X X X X
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-50 COMPD_REF Register Field Descriptions

Bit Field Type Reset Description
7 COMPD_Mode RW 0 Comparator Mode:
0: PGOOD Mode
1: Comparator Mode
6:3 COMPD_DVS[3:0] RW 0000 Comparator Window Voltage Shifting:
% deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V
0000 = + 3% or 1.05 V
0001 = + 2% or 1 V
0010 = + 1% or 0.975 V
0011 = + 0% or 0.95 V
0100 = - 1% or 0.9 V
0101 = - 2% or 0.875 V
0110 = - 3% or 0.85 V
0111 = - 4% or 0.8 V
1000 = 0.75 V
1001 = 0.7 V
2:0 COMPD_VSEL[2:0] RW 000 Comparator Window Voltage Select:
000 = 1 V
001 = 1.2 V
010 = 1.5 V
011 = 1.8 V
100 = 1.1 V
101 = 1.35 V
110 = 3.3 V
111 = 2.5 V / 5 V

6.6.1.48 COMPE_REF Register (address = 0xE1) [reset = 00000000]

Figure 6-70 COMPE_REF Register Format
B7 B6 B5 B4 B3 B2 B1 B0
COMPE_MODE COMPE_DVS[3] COMPE_DVS[2] COMPE_DVS[1] COMPE_DVS[0] COMPE_VSEL[2] COMPE_VSEL[1] COMPE_VSEL[0]
X X X X X X X X
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-51 COMPE_REF Register Field Descriptions

Bit Field Type Reset Description
7 COMPE_Mode RW 0 Comparator Mode:
0: PGOOD Mode
1: Comparator Mode
6:3 COMPE_DVS[3:0] RW 0000 Comparator Window Voltage Shifting:
% deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V
0000 = + 3% or 1.05 V
0001 = + 2% or 1 V
0010 = + 1% or 0.975 V
0011 = + 0% or 0.95 V
0100 = - 1% or 0.9 V
0101 = - 2% or 0.875 V
0110 = - 3% or 0.85 V
0111 = - 4% or 0.8 V
1000 = 0.75 V
1001 = 0.7 V
2:0 COMPE_VSEL[2:0] RW 000 Comparator Window Voltage Select:
000 = 1 V
001 = 1.2 V
010 = 1.5 V
011 = 1.8 V
100 = 1.1 V
101 = 1.35 V
110 = 3.3 V
111 = 2.5 V / 5 V

6.6.1.49 COMPF_REF Register (address = 0xE2) [reset = 00000000]

Figure 6-71 COMPF_REF Register Format
B7 B6 B5 B4 B3 B2 B1 B0
COMPF_MODE COMPF_DVS[3] COMPF_DVS[2] COMPF_DVS[1] COMPF_DVS[0] COMPF_VSEL[2] COMPF_VSEL[1] COMPF_VSEL[0]
X X X X X X X X
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-52 COMPF_REF Register Field Descriptions

Bit Field Type Reset Description
7 COMPF_Mode RW 0 Comparator Mode:
0: PGOOD Mode
1: Comparator Mode
6:3 COMPF_DVS[3:0] RW 0000 Comparator Window Voltage Shifting:
% deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V
0000 = + 3% or 1.05 V
0001 = + 2% or 1 V
0010 = + 1% or 0.975 V
0011 = + 0% or 0.95 V
0100 = - 1% or 0.9 V
0101 = - 2% or 0.875 V
0110 = - 3% or 0.85 V
0111 = - 4% or 0.8 V
1000 = 0.75 V
1001 = 0.7 V
2:0 COMPF_VSEL[2:0] RW 000 Comparator Window Voltage Select:
000 = 1 V
001 = 1.2 V
010 = 1.5 V
011 = 1.8 V
100 = 1.1 V
101 = 1.35 V
110 = 3.3 V
111 = 2.5 V / 5 V

6.6.1.50 COMPG_REF Register (address = 0xE3) [reset = 00000000]

Figure 6-72 COMPG_REF Register Format
B7 B6 B5 B4 B3 B2 B1 B0
COMPG_MODE COMPG_DVS[3] COMPG_DVS[2] COMPG_DVS[1] COMPG_DVS[0] COMPG_VSEL[2] COMPG_VSEL[1] COMPG_VSEL[0]
X X X X X X X X
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-53 COMPG_REF Register Field Descriptions

Bit Field Type Reset Description
7 COMPG_Mode RW 0 Comparator Mode:
0: PGOOD Mode
1: Comparator Mode
6:3 COMPG_DVS[3:0] RW 0000 Comparator Window Voltage Shifting:
% deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V
0000 = + 3% or 1.05 V
0001 = + 2% or 1 V
0010 = + 1% or 0.975 V
0011 = + 0% or 0.95 V
0100 = - 1% or 0.9 V
0101 = - 2% or 0.875 V
0110 = - 3% or 0.85 V
0111 = - 4% or 0.8 V
1000 = 0.75 V
1001 = 0.7 V
2:0 COMPG_VSEL[2:0] RW 000 Comparator Window Voltage Select:
000 = 1 V
001 = 1.2 V
010 = 1.5 V
011 = 1.8 V
100 = 1.1 V
101 = 1.35 V
110 = 3.3 V
111 = 2.5 V / 5 V

6.6.1.51 COMPH_REF Register (address = 0xE4) [reset = 00000000]

Figure 6-73 COMPH_REF Register Format
B7 B6 B5 B4 B3 B2 B1 B0
COMPH_DISCHG COMPH_DVS[3] COMPH_DVS[2] COMPH_DVS[1] COMPH_DVS[0] COMPH_VSEL[2] COMPH_VSEL[1] COMPH_VSEL0]
0 X X X X X X X
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-54 COMPH_REF Register Field Descriptions

Bit Field Type Reset Description
7 COMPH_DISCHG RW 0 Comparator H Discharge value
0: No discharge
1: 100 Ω
6:3 COMPH_DVS[3:0] RW 0000 Comparator Window Voltage Shifting:
% deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V
0000 = + 3% or 1.05 V
0001 = + 2% or 1 V
0010 = + 1% or 0.975 V
0011 = + 0% or 0.95 V
0100 = - 1% or 0.9 V
0101 = - 2% or 0.875 V
0110 = - 3% or 0.85 V
0111 = - 4% or 0.8 V
1000 = 0.75 V
1001 = 0.7 V
2:0 COMPH_VSEL[2:0] RW 000 Comparator Window Voltage Select:
000 = 1 V
001 = 1.2 V
010 = 1.5 V
011 = 1.8 V
100 = 1.1 V
101 = 1.35 V
110 = 3.3 V
111 = 2.5 V / 5 V

6.6.1.52 PWFAULT_MASK1 Register (address = 0xE5) [reset = 00000000]

Figure 6-74 PWFAULT_MASK1 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V4_FLTmsK V5_FLTmsK V6_FLTmsK V7_FLTmsK V8_FLTmsK V9_FLTmsK V10_FLTmsK V13_FLTmsK
0 0 0 0 0 0 0 1
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-55 PWFAULT_MASK1 Register Field Descriptions

Bit Field Type Reset Description
7 V4_FLTmsK RW 0 V4 Power Fault Masked
0: Not Masked
1: Masked
6 V5_FLTmsK RW 0 V5 Power Fault Masked
0: Not Masked
1: Masked
5 V6_FLTmsK RW 0 V6 Power Fault Masked
0: Not Masked
1: Masked
4 V7_FLTmsK RW 0 V7 Power Fault Masked
0: Not Masked
1: Masked
3 V8_FLTmsK RW 0 V8 Power Fault Masked
0: Not Masked
1: Masked
2 V9_FLTmsK RW 0 V9 Power Fault Masked
0: Not Masked
1: Masked
1 V10_FLTmsK RW 0 V10 Power Fault Masked
0: Not Masked
1: Masked
0 V13_FLTmsK RW 0 V13 Power Fault Masked
0: Not Masked
1: Masked

6.6.1.53 PWFAULT_MASK2 Register (address = 0xE6) [reset = 00000000]

Figure 6-75 PWFAULT_MASK2 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_PWFAULT_MASK2[5] RESERVED_PWFAULT_MASK2[4] RESERVED_PWFAULT_MASK2[3] RESERVED_PWFAULT_MASK2[2] RESERVED_PWFAULT_MASK2[1] RESERVED_PWFAULT_MASK2[0] V11_FLTmsK V12_FLTmsK
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-56 PWFAULT_MASK2 Register Field Descriptions

Bit Field Type Reset Description
7:2 RESERVED_PWFAULT_MASK2[5:0] 000000 Read Always Returns '1'
1 V11_FLTmsK 0 V11 Power Fault Masked
0: Not Masked
1: Masked
0 V12_FLTmsK 0 V12 Power Fault Masked
0: Not Masked
1: Masked

6.6.1.54 PGOOD_STAT1 Register (address = 0xE7) [reset = 00000000]

Figure 6-76 PGOOD_STAT1 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V13_PGOOD V10_PGOOD V9_PGOOD V8_PGOOD V7_PGOOD V6_PGOOD V5_PGOOD V4_PGOOD
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-57 PGOOD_STAT1 Register Field Descriptions

Bit Field Type Reset Description
7 V13_PGOOD R 0 V13 PGOOD STATUS
0: Fail
1: Pass
6 V10_PGOOD R 0 V10 PGOOD STATUS
0: Fail
1: Pass
5 V9_PGOOD R 0 V9 PGOOD STATUS
0: Fail
1: Pass
4 V8_PGOOD R 0 V8 PGOOD STATUS
0: Fail
1: Pass
3 V7_PGOOD R 0 V7 PGOOD STATUS
0: Fail
1: Pass
2 V6_PGOOD R 0 V6 PGOOD STATUS
0: Fail
1: Pass
1 V5_PGOOD R 0 V5 PGOOD STATUS
0: Fail
1: Pass
0 V4_PGOOD R 0 V4 PGOOD STATUS
0: Fail
1: Pass

6.6.1.55 PGOOD_STAT2 Register (address = 0xE8) [reset = 00000000]

Figure 6-77 PGOOD_STAT2 Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_PGOOD_STAT2[2] RESERVED_PGOOD_STAT2[1] RESERVED_PGOOD_STAT2[0] V12_PGOOD V11_PGOOD V11_SPGD V8_SPGD V6_SPGD
0 0 0 0 0 0 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-58 PGOOD_STAT2 Register Field Descriptions

Bit Field Type Reset Description
7:5 RESERVED_PGOOD_STAT2[2:0] R 000 Read Always Returns '1'
4 V12_PGOOD R 0 V12 PGOOD STATUS
0: Fail
1: Pass
3 V11_PGOOD R 0 V11 PGOOD STATUS
0: Fail
1: Pass
2 V11_SPGD R 0 V11S PGOOD STATUS
0: Fail
1: Pass
1 V8_SPGD R 0 V8S PGOOD STATUS
0: Fail
1: Pass
0 V6_SPGD R 0 V6S PGOOD STATUS
0: Fail
1: Pass

6.6.1.56 MISC_BITS Register (address = 0xE9) [reset = 00010000]

Figure 6-78 MISC_BITS Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V13_PIN_OVR MV13EN V6_PIN_OVR MV6EN msLP_S3ZPG msLP_SUSZPG BC_ACOK_EN V13DISCHG
0 0 0 0 0 0 1 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-59 MISC_BITS Register Field Descriptions

Bit Field Type Reset Description
7 V13_PIN_OVR RW 0 V13 ENABLE PIN Over Ride
0: V13 is OFF if MV13EN is '1'
1: V13 is ON if MV13EN is '1'
6 MV13EN RW 0 V13 Enable Pin Mask
0: DDR_VT_CTRL Pin controls V13
1: V13_EN_PIN Bit [Bit(3)] controls V13
5 V6_PIN_OVR RW 0 V6 ENABLE PIN Over Ride
0: V6 Pin controls V6
1: V6 is ON if VREN PIN MASK = '0'
4 MV6EN RW 1 V6 Enable Pin Mask
0: VR Enable Pin controls VR enable
1: VR Enable Pin masked V*CTLV controls VR enable
3 msLP_S3ZPG RW 0 SLP_S3Z is part of the power good tree
0: SLP_S3Z is part of Power Good Tree
1: SLP_S3Z is masked and set to 1 (not part of the Power Good tree)
2 msLP_SUSZPG RW 0 SLP_SUSZ is part of the power good tree
0: SLP_SUSZ is part of Power Good Tree
1: SLP_SUSZ is masked and set to 1 (not part of the Power Good tree)
1 BC_ACOK_EN RW 1 Enables BC_ACOK output out of LVA pin. The in put is ACOK pin, instead of ENLVA pin.
0: LVA pin is not BC_ACOK, and ENLVA is the input for LVA output, behaving as a general purpose level-shifter.
1: LVA pin is BC_ACOK, and ACOK is the input, and ENLVA is not functional. BC_ACOK is a level-shifted version of ACOK.
0 V13DISCHG RW 0 V0.6DX discharge resistance (V13)
0: No discharge
1: 100 Ω

6.6.1.57 STDBY_CTRL Register (address = 0xEA) [reset = 11111110]

Figure 6-79 STDBY_CTRL Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_STDBY_CTRL[4] RESERVED_STDBY_CTRL[3] RESERVED_STDBY_CTRL[2] RESERVED_STDBY_CTRL[1] RESERVED_STDBY_CTRL[0] EN_VCOMP_10U VCOMPEN QLSLPS0_ACTIVE
1 1 1 1 1 1 1 0
R R R R R RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-60 STDBY_CTRL Register Field Descriptions

Bit Field Type Reset Description
7:3 RESERVED_STDBY_CTRL[4:0] R 11111 Read Always Returns '1'
2 EN_VCOMP_10U RW 1 VCOMP Current Source Control bit:
0: Disable
1: Enable
1 VCOMPEN RW 1 VCOMP Enable Control bit:
0: Disable
1: Enable
0 QLSLPS0_ACTIVE RW 0 SLP_S0 & DDR_VTT_CTRL Detect logic Control
0: Normal Operation DELAY_ALL_SYS_PG is used in QSTANDBY# (SLP_S0#)
1: DELAY_ALL_SYS_PG is ignored for QSTANDBY# (SLP_S0#)

6.6.1.58 TEMPCRIT Register (address = 0xEB) [reset = 00000000]

Figure 6-80 TEMPCRIT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_TEMPCRIT[1] RESERVED_TEMPCRIT[0] LDO1_CRIT VR5_CRIT VR4_CRIT VR3_CRIT VR2_CRIT VR1_CRIT
0 0 0 0 0 0 0 0
R R RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-61 TEMPCRIT Register Field Descriptions

Bit Field Type Reset Description
7:6 RESERVED_TEMPCRIT[1:0] R 00 Read Always Returns '0'
5 LDO1_CRIT RW 0 LDO1 CRITTEMP
0: Not asserted,
1: Asserted, Regulator at critical temperature, write '1' to clear
4 VR5_CRIT RW 0 VR5 CRITTEMP
0: Not asserted
1: Asserted, Regulator at critical temperature, write '1' to clear
3 VR4_CRIT RW 0 VR4 CRITTEMP
0: Not asserted
1: Asserted, Regulator at critical temperature, write '1' to clear
2 VR3_CRIT RW 0 VR3 CRITTEMP
0: Not asserted
1: Asserted, Regulator at critical temperature, write '1' to clear
1 VR2_CRIT RW 0 VR2 CRITTEMP
0: Not asserted
1: Asserted, Regulator at critical temperature, write '1' to clear
0 VR1_CRIT RW 0 VR1 CRITTEMP
0: Not asserted
1: Asserted, Regulator at critical temperature, write '1' to clear

6.6.1.59 TEMPHOT Register (address = 0xEC) [reset = 00000000]

Figure 6-81 TEMPHOT Register Format
B7 B6 B5 B4 B3 B2 B1 B0
RESERVED_TEMPHOT[1] RESERVED_TEMPHOT[0] LDO1_HOT VR5_HOT VR4_HOT VR3_HOT VR2_HOT VR1_HOT
0 0 0 0 0 0 0 0
R R RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-62 TEMPHOT Register Field Descriptions

Bit Field Type Reset Description
7:6 RESERVED_TEMPHOT[1:0] R 00 Read Always Returns '1'
5 LDO1_HOT RW 0 LDO1 HOT TEMP
0: Not asserted
1: Asserted, write '1' to clear
4 VR5_HOT RW 0 VR5 HOT TEMP
0: Not asserted
1: Asserted, write '1' to clear
3 VR4_HOT RW 0 VR4 HOT TEMP
0: Not asserted
1: Asserted, write '1' to clear
2 VR3_HOT RW 0 VR3 HOT TEMP
0: Not asserted
1: Asserted, write '1' to clear
1 VR2_HOT RW 0 VR2 HOT TEMP
0: Not asserted
1: Asserted, write '1' to clear
0 VR1_HOT RW 0 VR1 HOT TEMP
0: Not asserted
1: Asserted, write '1' to clear

6.6.1.60 VREN_PIN_OVR Register (address = 0xEE) [reset = 00000000]

Figure 6-82 VREN_PIN_OVR Register Format
B7 B6 B5 B4 B3 B2 B1 B0
V12_PIN_OVR V11_PIN_OVR V10_PIN_OVR V9_PIN_OVR V8_PIN_OVR V7_PIN_OVR V5_PIN_OVR V4_PIN_OVR
0 0 0 0 0 0 0 0
RW RW RW RW RW RW RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-63 VREN_PIN_OVR Register Field Descriptions

Bit Field Type Reset Description
7 V12_PIN_OVR RW 0 V12 ENABLE PIN Over Ride
0: V12 Pin controls V12
1: V12 is ON if VREN PIN MASK = '0'
6 V11_PIN_OVR RW 0 V11 ENABLE PIN Over Ride
0: V11 Pin controls V11
1: V11 is ON if VREN PIN MASK = '0'
5 V10_PIN_OVR RW 0 V10 ENABLE PIN Over Ride
0: V10 Pin controls V10
1: V10 is ON if VREN PIN MASK = '0'
4 V9_PIN_OVR RW 0 V9 ENABLE PIN Over Ride
0: V9 Pin controls V9
1: V9 is ON if VREN PIN MASK = '0'
3 V8_PIN_OVR RW 0 V8 ENABLE PIN Over Ride
0: V8 Pin controls V8
1: V8 is ON if VREN PIN MASK = '0'
2 V7_PIN_OVR RW 0 V7 ENABLE PIN Over Ride
0: V7 Pin controls V7
1: V7 is ON if VREN PIN MASK = '0'
1 V5_PIN_OVR RW 0 V5 ENABLE PIN Over Ride
0: V5 Pin controls V5
1: V5 is ON if VREN PIN MASK = '0'
0 V4_PIN_OVR RW 0 V4 ENABLE PIN Over Ride
0: V4 Pin controls V4
1: V4 is ON if VREN PIN MASK = '0'