SLVSAA2D March   2010  – January  2016 TPS65182B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Data Transmission Timing
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Modes of Operation
      2. 7.3.2  Mode Transistions
      3. 7.3.3  Wake-Up and Power Up Sequencing
      4. 7.3.4  Dependencies Between Rails
      5. 7.3.5  Soft-Start
      6. 7.3.6  VCOM Adjustment
      7. 7.3.7  VPOS and VNEG Supply Tracking
      8. 7.3.8  Fault Handling and Recovery
      9. 7.3.9  Power Good Pin
      10. 7.3.10 Panel Temperature Monitoring
      11. 7.3.11 NTC Bias Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Bus Operation
    5. 7.5 Register Maps
      1. 7.5.1 Thermistor Readout (TMST_VALUE) Register (offset = 0x00h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
TPS65182 TPS65182B po_lvsaa2.gif

Pin Functions

PIN I/O DESCRIPTION(1)
NO. NAME
1 VREF O Filter pin for 2.25-V internal reference to ADC
2 N/C — Not connected
3 VNEG O Negative supply output pin for panel source drivers
4 VNEG_IN I Input pin for LDO2 (VNEG)
5 WAKEUP I Wake up pin (active high). Pull this pin high to wake up from sleep mode.
6 DGND — Digital ground
7 INT_LDO2 O Internal supply (digital circuitry) filter pin
8 AGND1 — Analog ground for general analog circuitry
9 INT_LDO1 O Internal supply (analog circuitry) filter pin
10 VIN I Input power supply to general circuitry
11 VCOM_XADJ I Analog input for conventional VCOM setup method. Tie this pin to ground if VCOM is set through I2C interface.
12 VCOM_CTRL I VCOM_PANEL gate driver enable (active high)
13 N/C — Not connected
14 VCOM_PANEL O Panel common-voltage output pin
15 VCOM O Filter pin for panel common-voltage driver
16 VCOM_PWR I Internal supply input pin to VCOM buffer. Connect to the output of DCDC2.
17 SCL I Serial interface (I2C) clock input
18 SDA I/O Serial interface (I2C) data input/output
19 PWR3 I Enable pin for CP1 (VDDH) (active high)
20 PWR2 I Enable pin for LDO1 (VPOS) (active high)
21 PWR1 I Enable pin for CP2 (VEE) (active high)
22 PWR0 I Enable pin for LDO2 (VNEG) and VCOM (active high)
24 PWR_GOOD O Open drain power good output pin (active low)
25 VN_SW O Inverting buck-boost converter switch out (DCDC2)
26 N/C — Not connected
27 VIN_P I Input power supply to inverting buck-boost converter (DCDC2)
28 VN I Feedback pin for inverting buck-boost converter (DCDC2)
29 VEE_IN I Input supply pin for CP1 (VEE)
30 VEE_DRV O Driver output pin for negative charge pump (CP2)
31 VEE_D O Base voltage output pin for negative charge pump (CP2)
32 VEE_FB I Feedback pin for negative charge pump (CP2)
33 PGND2 — Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps
34 VDDH_FB I Feedback pin for positive charge pump (CP1)
35 VDDH_D O Base voltage output pin for positive charge pump (CP1)
36 VDDH_DRV O Driver output pin for positive charge pump (CP1)
37 VDDH_IN I Input supply pin for positive charge pump (CP1)
38 N/C — Not connected
39 N/C — Not connected
40 VB_SW O Boost converter switch out (DCDC1)
41 PGND3 — Power ground for DCDC1
42 VB I Feedback pin for boost converter (DCDC1)
43 VPOS_IN I Input pin for LDO1 (VPOS)
44 VPOS O Positive supply output pin for panel source drivers
45 N/C — Not connected
46 N/C — Not connected
47 TS I Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor between this pin and AGND2.
48 AGND2 — Reference point to external thermistor and linearization resistor
23 PowerPad (PBKG) — Die substrate/thermal pad. Connect to VN with short, wide trace. Wide copper trace will improve heat dissipation. PowerPad must not be connected to ground.
(1) There will be 0-ns, 93.75-µs, 62.52-µs of deglitch for PWRx, WAKEUP, and VCOM_CTRL, respectively.