The TPS65219-Q1 allows flexible sequencing of the rails. The order of the rails, including GPO1, GPO2, GPIO for the external rails, and the nRSTOUT pin is defined by the NVM. Prior to starting the power-up sequence, the device checks if the voltage on all rails fell below the SCG-threshold to avoid starting into a pre-biased rail. The sequence is timing based. In addition, the previous rail must have passed the UV-threshold, else the subsequent rail is not enabled. If UV is masked, the sequence proceeds even if the UV-threshold is not reached. GPO1, GPO2, GPIO, and LDOs configured in bypass- or LSW-mode are not monitored for under-voltage, thus their outputs do not gate subsequent rails.

In case the sequence is interrupted due to an unmasked fault on a rail, the device powers down. The TPS65219-Q1 attempts to power up two more times. If both of those re-tries fail to enter ACTIVE state, the device remains in INITIALIZE state until VSYS is power-cycled. While it is encouraged to keep this retry-counter active, one can disable it by setting bit MASK_RETRY_COUNT in INT_MASK_UV register.

To disable the retry-counter, set bit MASK_RETRY_COUNT in INT_MASK_UV register. When set, the device attempts to retry infinitely.

The TPS65219-Q1 allows to configure the power-down sequence independent from the power-up sequence. The sequences are configured in the non-volatile memory.

At initial power-up, the device monitors the VSYS supply voltage and allows power-up and transition to INITIALZE state only if VSYS passed the VSYS_{POR_Rising} threshold.

The power-up sequence is configured as follows:

• The slot (respectively the position in the sequence) for each rail and GPO1, GPO2, GPIO, and nRSTOUT is defined using the corresponding *_SEQUENCE_SLOT registers, the four MSB for the power-up sequence, the four LSB for the power-down sequence.
• The duration of each slot is defined in the POWER_UP_SLOT_DURATION_x registers and can be configured as 0 ms, 1.5 ms, 3 ms or 10 ms. In total, 16 slots can be configured, allowing the sequence to span over multiple TPS65219-Q1-devices if more rails need to be supported.
• In addition to the timing as defined above, the power-up-sequence is also gated by the UV-monitor: a subsequent rail only gets enabled after the previous one passed the under-voltage threshold (unless UV is masked). If a rail has not reached the UV-threshold by the end of t_RAMP (respectively t_{RAMP_LSW}, t_{RAMP_SLOW}, t_{RAMP_FAST}), the sequence is aborted and the device sequences down at the end of the slot-duration. For the respective rail, the device sets INT_BUCK_x_y_IS_SET respectively INT_LDO_x_y_IS_SET bit in INT_SOURCE register and BUCKx_UV respectively LDOx_UV bit in INT_BUCK_x_y respectively INT_LDO_x_y register as well as bit TIMEOUT in the INT_TIMEOUT_RV_SD register.
• The initiation of the sequence is gated by the successful discharge of all rails, irrespective if enabled during the sequence or not. If the device is unable to discharge all rails below the SCG-threshold, the device sets INT_BUCK_x_y_IS_SET respectively INT_LDO_x_y_IS_SET bit in INT_SOURCE register and BUCKx_RV respectively LDOx_RV bit if the residual voltage is still present after 4 ms to 5 ms and the device remains in INITIALIZE state.
• The initiation of the sequence is gated by the die-temperature: if any one of the WARM detections is unmasked, the device does not power-up until the temperature on all sensors fell below T_{WARM_falling} threshold if INITIALIZE state was entered due to a thermal event, respectively until the temperature on all sensors is below T_{WARM_rising} threshold if INITIALIZE state was entered from OFF-state. If all thermal sensors are masked (WARM detection not causing a power-down), the device does not power-up until the temperature on all sensors is below T_{HOT_falling} threshold

An ON-request is deglitched to not trigger on noise. After the deglitch time, the device takes approximately 300 μs until the first slot of the sequence starts. In case discharging of pre-biased rails is not completed by that time, the start of the sequence is further gated until all rails have discharged below SCG-voltage level.

Below graphic shows the power-up-sequence for NVM-ID 0x01, revision 0x2 as an example:

Figure 7-2 Power-up sequencing (example)

For details on ON-requests please see Push Button and Enable Input (PB/EN/VSENSE).