SLVSAA4G June   2010  – February 2018 TPS65251

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjustable Switching Frequency
      2. 8.3.2  Synchronization
      3. 8.3.3  Out-of-Phase Operation
      4. 8.3.4  Delayed Start-Up
      5. 8.3.5  Soft-Start Time
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Input Capacitor
      8. 8.3.8  Bootstrap Capacitor
      9. 8.3.9  Error Amplifier
      10. 8.3.10 Loop Compensation
      11. 8.3.11 Slope Compensation
      12. 8.3.12 Powergood
      13. 8.3.13 Current Limit Protection
      14. 8.3.14 Overvoltage Transient Protection
      15. 8.3.15 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Loop Compensation Circuit
        2. 9.2.2.2  Selecting the Switching Frequency
        3. 9.2.2.3  Output Inductor Selection
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Input Capacitor
        6. 9.2.2.6  Soft-Start Capacitor
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Adjustable Current Limiting Resistor Selection
        9. 9.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 9.2.2.10 Compensation
        11. 9.2.2.11 3.3-V and 6.5-V LDO Regulators
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.1 Loop Compensation Circuit

A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60 and 90 degrees, or type III (Rc, Cc and Cff) to improve the converter transient response. CRoll adds a high frequency pole to attenuate high-frequency noise when needed. It may also prevent noise coupling from other rails if there is possibility of cross coupling in between rails when layout is very compact.

TPS65251 loop_comp1_lvsaa4.gifFigure 22. Loop Compensation

To calculate the external compensation components use Table 1:

Table 1. Design Guideline for the Loop Compensation

TYPE II CIRCUITTYPE III CIRCUIT
Select switching frequency that is appropriate for application depending on L, C sizes, output ripple, EMI concerns and etc. Switching frequencies between 500 kHz and 1 MHz give best trade off between performance and cost. When using smaller L and Cs, switching frequency can be increased. To optimize efficiency, switching frequency can be lowered. Type III circuit recommended for switching frequencies higher than 500 kHz.
Select cross over frequency (fc) to be less than 1/5 to 1/10 of switching frequency. Suggested
fc = fs/10		 Suggested
fc = fs/10
Set and calculate Rc.
Equation 7. TPS65251 eq6_rc_lvsaa4.gif
Equation 8. TPS65251 eq6a_rc_lvsaa4.gif
Calculate Cc by placing a compensation zero at or before the converter dominant pole
Equation 9. TPS65251 eq7a_fp_lvsaa4.gif
Equation 10. TPS65251 eq7_cc_lvsaa4.gif
Equation 11. TPS65251 eq7_cc_lvsaa4.gif
Add CRoll if needed to remove large signal coupling to high impedance COMP node. Make sure that
Equation 12. TPS65251 eq8_fproll_lvsaa4.gif
is at least twice the cross over frequency.
Equation 13. TPS65251 eq9_croll_lvsaa4.gif
Equation 14. TPS65251 eq9_croll_lvsaa4.gif
Calculate Cff compensation zero at low frequency to boost the phase margin at the crossover frequency. Make sure that the zero frequency (fzff is smaller than soft-start equivalent frequency (1/Tss). NA
Equation 15. TPS65251 eq10_cff_lvsaa4.gif