SLVSCQ2 July   2015 TPS65400-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Operational Parameters
    8. 7.8 Package Dissipation Ratings
    9. 7.9 Typical Characteristics: System Efficiency
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Startup Timing and Power Sequencing
        1. 8.3.1.1 Startup Timing
        2. 8.3.1.2 External Sequencing
        3. 8.3.1.3 Internal Sequencing
      2. 8.3.2  UVLO and Precision Enables
      3. 8.3.3  Soft-Start and Prebiased Startup
        1. 8.3.3.1 Analog Soft-Start (Default) and Digital Soft-Start
        2. 8.3.3.2 Soft-Start Capacitor Selection
      4. 8.3.4  PWM Switching Frequency Selection
      5. 8.3.5  Clock Synchronization
      6. 8.3.6  Phase Interleaving
      7. 8.3.7  Fault Handling
      8. 8.3.8  OCP for SW1 to SW4
      9. 8.3.9  Overcurrent Protection for SW1 to SW4 in Current Sharing Operation
      10. 8.3.10 Recovery on Power Loss
      11. 8.3.11 Feedback Compensation
      12. 8.3.12 Adjusting Output Voltage
      13. 8.3.13 Digital Interface - PMBus
      14. 8.3.14 Initial Configuration
    4. 8.4 Device Functional Modes
      1. 8.4.1 CCM Operation Mode
      2. 8.4.2 CCM/DCM Operation Mode
      3. 8.4.3 Current Sharing Mode
    5. 8.5 Register Maps
      1. 8.5.1 PMBus
        1. 8.5.1.1 Overview
        2. 8.5.1.2 PMBus Protocol
          1. 8.5.1.2.1  PMBus Protocol
          2. 8.5.1.2.2  Transactions (No PEC)
          3. 8.5.1.2.3  Addressing
          4. 8.5.1.2.4  Startup
          5. 8.5.1.2.5  Bus Speed
          6. 8.5.1.2.6  I2CALERT Terminal
          7. 8.5.1.2.7  CONTROL Terminal
          8. 8.5.1.2.8  Packet Error Checking
          9. 8.5.1.2.9  Group Commands
          10. 8.5.1.2.10 Unsupported Features
      2. 8.5.2 PMBus Register Descriptions
        1. 8.5.2.1 Overview
        2. 8.5.2.2 Memory Model
        3. 8.5.2.3 Data Formats
        4. 8.5.2.4 Fault Monitoring
      3. 8.5.3 PMBus Core Commands
        1. 8.5.3.1  (00h) PAGE
        2. 8.5.3.2  (01h) OPERATION
        3. 8.5.3.3  (03h) CLEAR_FAULTS
        4. 8.5.3.4  (10h) WRITE_PROTECT
        5. 8.5.3.5  (11h) STORE_DEFAULT_ALL
        6. 8.5.3.6  (19h) CAPABILITY
        7. 8.5.3.7  (78h) STATUS_BYTE
        8. 8.5.3.8  (79h) STATUS_WORD
        9. 8.5.3.9  (7Ah) STATUS_VOUT
        10. 8.5.3.10 (80h) STATUS_MFR_SPECIFIC
        11. 8.5.3.11 (98h) PMBUS_REVISION
        12. 8.5.3.12 (ADh) IC_DEVICE_ID
        13. 8.5.3.13 (AEh) IC_DEVICE_REV
      4. 8.5.4 Manufacturer-Specific Commands
        1. 8.5.4.1  (D0h) USER_DATA_BYTE_00
        2. 8.5.4.2  (D1h) USER_DATA_BYTE_01
        3. 8.5.4.3  (D2h) PIN_CONFIG_00
        4. 8.5.4.4  (D3h) PIN_CONFIG_01
        5. 8.5.4.5  (D4h) SEQUENCE_CONFIG
        6. 8.5.4.6  (D5h) SEQUENCE_ORDER
        7. 8.5.4.7  (D6h) IOUT_MODE
        8. 8.5.4.8  (D7h) FREQUENCY_PHASE
        9. 8.5.4.9  (D8h) VREF_COMMAND
        10. 8.5.4.10 (D9h) IOUT_MAX
        11. 8.5.4.11 (DAh) USER_RAM_00
        12. 8.5.4.12 (DBh) SOFT_RESET
        13. 8.5.4.13 (DCh) RESET_DELAY
        14. 8.5.4.14 (DDh) TON_TOFF_DELAY
        15. 8.5.4.15 (DEh) TON_TRANSITION_RATE
        16. 8.5.4.16 (DFh) VREF_TRANSITION_RATE
        17. 8.5.4.17 (F0h) SLOPE_COMPENSATION
        18. 8.5.4.18 (F1h) ISENSE_GAIN
        19. 8.5.4.19 (FCh) DEVICE_CODE
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Internal Operation Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Component Selection
            1. 9.2.1.2.1.1 Output Inductor Selection
            2. 9.2.1.2.1.2 Output Capacitor Selection
          2. 9.2.1.2.2 Internal Operation With Some Switchers Disabled
          3. 9.2.1.2.3 Internal Operation With All Switchers Enabled
          4. 9.2.1.2.4 Example Configuration
          5. 9.2.1.2.5 Unused Switchers
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Current Sharing Typical Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing Timing Example
      3. 9.2.3 External Sequencing Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 External Sequencing Through PG Pins
          2. 9.2.3.2.2 External Sequencing Through SW
          3. 9.2.3.2.3 Example Configuration
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
      2. 12.1.2 Related Parts
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

  • PMBus Power System Management Protocol Specification Part I – General Requirements, Transport and Electrical Interface, Revision 1.2, dated 6 September 2010, published by the Power Management Bus Implementers Forum (http://pmbus.org/Specifications).

12.1.2 Related Parts

PART NUMBER DESCRIPTION COMMENTS
TPS65262 4.5- to 18-V, triple buck with dual adjustable LDOs Triple buck 3-A/1-A/1-A output current, dual LDOs 100-mA/200-mA output current, automatic power sequencing
TPS65263 4.5- to 18-V, triple buck with I2C interface Triple buck 3-A/2-A/2-A output current, I2C-controlled dynamic voltage scaling (DVS)
TPS65651-1/2/3 4.5- to 18-V, triple buck with different PGOOD deglitch time Triple buck 3-A/2-A/2-A output current, support 1-s, 32-ms, and 256-ms PGOOD deglitch time, adjustable current limit setting by external resistor
TPS65287 4.5- to 18-V, triple buck with power switch and push-button control Triple buck 3-A/2-A/2-A output current, up to 2.1-A USB power with overcurrent setting by external resistor, push-button control for intelligent system power-on/power-off operation
TPS65288 4.5- to 18-V, triple buck with dual power switches Triple buck 3-A/2-A/2-A output current, 2 USB power switches current limiting at typical 1.2 A (0.8/1/1.4/1.6/1.8/2/2.2 A available with manufacture trim options)

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.