SLVSCY2A March   2015  – January 2016 TPS65632

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Boost Converter 1 (VPOS)
        1. 7.3.1.1 V(POS) Boost Output Sense (FBS Pin)
      2. 7.3.2 Inverting Buck-Boost Converter (VNEG)
        1. 7.3.2.1 Programming VNEG
        2. 7.3.2.2 Controlling VNEG Transition Time
      3. 7.3.3 Boost Converter 2 (AVDD)
      4. 7.3.4 Soft Start and Start-Up Sequence
      5. 7.3.5 Enable (CTRL)
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Short-Circuit Protection
        1. 7.3.7.1 Short Circuits During Operation
        2. 7.3.7.2 Short Circuits During Start Up
      8. 7.3.8 Output Discharge During Shut Down
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VI < 2.9 V
      2. 7.4.2 Operation with VI ≈ VPOS (Diode Mode)
      3. 7.4.3 Operation with CTRL
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Ordering Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS65632 device is intended to supply the main analog supplies required by AMOLED displays. VPOS is fixed at 4.6 V, but VNEG can be programmed using the CTRL pin to voltages in the range –1.4 V to –5.4 V. The SELP2 pin can be used to set AVDD to either 5.8 V or 7.7 V. The device is highly integrated and requires few external components.

8.2 Typical Application

Figure 8 shows a typical application circuit suitable for supplying AMOLED displays in smartphone applications. The circuit is designed to operate from a single-cell Li-Ion battery and generates a positive output voltage VPOS of 4.6 V, a negative output voltage VNEG of –4.0 V, and a positive output voltage AVDD of 5.8 V or 7.7 V. The VPOS and VNEG outputs are each capable of supplying up to 300 mA of current, and the AVDD output of up to 30 mA.

TPS65632 schematic_02_slvscy2.eps Figure 8. Typical Application Circuit

8.2.1 Design Requirements

For this design example, use the parameters shown in Table 2

Table 2. Design Parameters

PARAMETER VALUE
Input voltage range 2.9 V to 4.5 V
Output voltage VPOS = 4.6 V
VNEG = –4.0 V
AVDD = 7.7 V
Current I(VPOS) = 300 mA
I(VNEG) = 300 mA
I(AVDD) = 30 mA
Switching Frequency f(SWP1) = 1.7 MHz
f(SWN) = 1.7 MHz
f(SWP2) = 1.7 MHz

8.2.2 Detailed Design Procedure

In order to maximize performance, the TPS65632 device has been optimized for use with a relatively narrow range of component values, and customers are strongly recommended to use the application circuits shown in Figure 8 with the components listed in Table 3 and Table 4.

8.2.2.1 Inductor Selection

The VPOS and VNEG converters have been optimized for use with 4.7-µH inductors and the AVDD boost converter has been optimized for use with 10-µH inductors. For optimum performance it is recommended that these values be used in all applications. Customers using different inductors than the ones in Table 3 are strongly recommended to characterize circuit performance fully before finalizing their design. Customers should pay particular attention to the inductors' saturation current and ensure it is adequate for their application's worst-case conditions (which may also be during start-up).

Table 3. Inductor Selection

REFERENCE DESIGNATOR VALUE MANUFACTURER PART NUMBER
L1, L3 4.7 µH Coilcraft XFL4020-4R7ML
L2 10 µH Coilmaster MMPP252012-100N

8.2.2.2 Capacitor Selection

The recommended capacitor values are shown in Table 4. Applications using less than the recommended capacitance (e.g. to save PCB area) may exhibit increased voltage ripple. In general, the lower the output current, the lower the necessary capacitance. Customers should be aware that ceramic capacitors of the kind typically used with the TPS65632 device exhibit dc bias effects, which means their effective capacitance under normal operating conditions may be significantly lower than their nominal capacitance value. Customers must ensure that the effective capacitance is sufficient for their application's performance requirements.

Table 4. Capacitor Selection

REFERENCE DESIGNATOR VALUE MANUFACTURER PART NUMBER
C1 3 × 10 µF Murata GRM21BR71A106KE51
C2, C6 10 µF Murata GRM21BR71A106KE51
C3 2 × 10 µF Murata GRM21BR71A106KE51
C4, C5 100 nF Murata GRM155B11A104KA01

8.2.3 Application Curves

Unless otherwise stated: TA = 25°C, VI = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, AVDD = 7.7 V; L1 = L3 = XFL4020-4R7ML, and L2 = MMPP252012-100N.

TPS65632 vpos_vneg_efficiency_slvscy2.png
Figure 9. VPOS and VNEG Combined Efficiency
TPS65632 vpos_line_regulation_slvscy2.png
Figure 11. VPOS Line Regulation
TPS65632 avdd_line_regulation_slvscy2.png
Figure 13. AVDD Line Regulation
TPS65632 vneg_load_regulation_slvscy2.png
Figure 15. VNEG Load Regulation
TPS65632 vpos_vneg_startup_slvscy2.gif
Figure 17. Start-Up: VPOS and VNEG
TPS65632 vpos_switch_waveforms_100m_slvscy2.gif
IPOS = 100 mA
Figure 19. Switch Pin, Inductor Current and Output Voltage Waveforms: VPOS
TPS65632 vneg_switch_waveforms_100m_slvscy2.gif
INEG = 100 mA
Figure 21. Switch Pin, Inductor Current and Output Voltage Waveforms: VNEG
TPS65632 avdd_switch_waveforms_10m_slvscy2.gif
IAVDD = 10 mA
Figure 23. Switch Pin, Inductor Current and Output Voltage Waveforms: AVDD
TPS65632 vpos_line_transient_slvscy2.png
VI = 3.0 V to 4.2 V in 50 µs
IPOS = 100 mA
Figure 25. VPOS Line Transient Response
TPS65632 avdd_line_transient_slvscy2.png
VI = 3.0 V to 4.2 V in 50 µs
IAVDD = 30 mA
Figure 27. AVDD Line Transient Response
TPS65632 vneg_load_transient_slvscy2.png
INEG = 10 mA to 100 mA in 100 ns
Figure 29. VNEG Load Transient Response
TPS65632 switching_frequency_slvscy2.png
IPOS = 100 mA INEG = 100 mA IAVDD = 30 mA
Figure 31. Switching Frequency
TPS65632 avdd_efficiency_slvscy2.png
Figure 10. AVDD Efficiency
TPS65632 vneg_line_regulation_slvscy2.png
Figure 12. VNEG Line Regulation
TPS65632 vpos_load_regulation_slvscy2.png
Figure 14. VPOS Load Regulation
TPS65632 avdd_load_regulation_slvscy2.png
Figure 16. AVDD Load Regulation
TPS65632 avdd_startup_slvscy2.gif
Figure 18. Start-Up: AVDD
TPS65632 vpos_switch_waveforms_300m_slvscy2.gif
IPOS = 300 mA
Figure 20. Switch Pin, Inductor Current and Output Voltage Waveforms: VPOS
TPS65632 vneg_switch_waveforms_300m_slvscy2.gif
INEG = 300 mA
Figure 22. Switch Pin, Inductor Current and Output Voltage Waveforms: VNEG
TPS65632 avdd_switch_waveforms_30m_slvscy2.gif
IAVDD = 30 mA
Figure 24. Switch Pin, Inductor Current and Output Voltage Waveforms: AVDD
TPS65632 vneg_line_transient_slvscy2.png
VI = 3.0 V to 4.2 V in 50 µs
INEG = 100 mA
Figure 26. VNEG Line Transient Response
TPS65632 vpos_load_transient_slvscy2.png
IPOS = 10 mA to 100 mA in 100 ns
Figure 28. VPOS Load Transient Response
TPS65632 avdd_load_transient_slvscy2.png
IAVDD = 10 mA to 30 mA in 100 ns
Figure 30. AVDD Load Transient Response