SWCS106F March   2013  – July 2016 TPS659119-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Characteristics
    5. 7.5  External Component Recommendation
    6. 7.6  I/O Pullup and Pulldown Characteristics
    7. 7.7  Digital I/O Voltage Electrical Characteristics
    8. 7.8  I2C Interface and Control Signals
    9. 7.9  Switching Characteristics—I2C Interface and Control Signals
    10. 7.10 Power Consumption
    11. 7.11 Power References and Thresholds
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 32-kHz RTC Clock
    14. 7.14 VRTC LDO
    15. 7.15 VIO SMPS
    16. 7.16 VDD1 SMPS
    17. 7.17 VDD2 SMPS
    18. 7.18 EXTCTRL
    19. 7.19 LDO1 AND LDO2
    20. 7.20 LDO3 and LDO4
    21. 7.21 LDO5
    22. 7.22 LDO6 and LDO7
    23. 7.23 LDO8
    24. 7.24 Timing Requirements for Boot Sequence Example
    25. 7.25 Power Control Timing Requirements
    26. 7.26 Device SLEEP State Control Timing Requirements
    27. 7.27 Supplies State Control Through EN1 and EN2 Timing Characteristics
    28. 7.28 VDD1 Supply Voltage Control Through EN1 Timing Requirements
    29. 7.29 Typical Characteristics
      1. 7.29.1 VIO SMPS Curves
      2. 7.29.2 VDD1 SMPS Curves
      3. 7.29.3 VDD2 SMPS Curves
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Reference
      2. 8.3.2 Power Resources
      3. 8.3.3 PWM and LED Generators
      4. 8.3.4 Dynamic-Voltage Frequency Scaling and Adaptive-Voltage Scaling Operation
      5. 8.3.5 32-kHz RTC Clock
      6. 8.3.6 Real-Time Clock (RTC)
      7. 8.3.7 Thermal Monitoring and Shutdown
      8. 8.3.8 Crystal Oscillator Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Embedded Power Controller
        1. 8.4.1.1 State-Machine
          1. 8.4.1.1.1 Device POWER-ON Enable Conditions
          2. 8.4.1.1.2 Device POWER ON Disable Conditions
          3. 8.4.1.1.3 Device SLEEP Enable Conditions
          4. 8.4.1.1.4 Device Reset Scenarios
        2. 8.4.1.2 Boot Configuration and Switch-On and Switch-Off Sequences
        3. 8.4.1.3 Control Signals
          1. 8.4.1.3.1  SLEEP
          2. 8.4.1.3.2  PWRHOLD
          3. 8.4.1.3.3  BOOT1
          4. 8.4.1.3.4  NRESPWRON, NRESPWRON2
          5. 8.4.1.3.5  CLK32KOUT
          6. 8.4.1.3.6  PWRON
          7. 8.4.1.3.7  INT1
          8. 8.4.1.3.8  EN2 and EN1
          9. 8.4.1.3.9  GPIO0-8
          10. 8.4.1.3.10 HDRST Input
          11. 8.4.1.3.11 PWRDN
          12. 8.4.1.3.12 Watchdog
          13. 8.4.1.3.13 Tracking LDO
    5. 8.5 Programming
      1. 8.5.1 Time-Calendar Registers
      2. 8.5.2 General Registers
      3. 8.5.3 Compensation Registers
      4. 8.5.4 Backup Registers
      5. 8.5.5 I2C Interface
        1. 8.5.5.1 Addressing
        2. 8.5.5.2 Access Protocols
          1. 8.5.5.2.1 Single-Byte Access
          2. 8.5.5.2.2 Multiple-Byte Access To Several Adjacent Registers
      6. 8.5.6 Interrupts
    6. 8.6 Register Maps
      1. 8.6.1 Functional Registers
      2. 8.6.2 TPS659119-Q1_FUNC_REG Register Mapping Summary
      3. 8.6.3 TPS659119-Q1_FUNC_REG Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-down Converter Input Capacitors
        2. 9.2.2.2 Step-down Converter Output Capacitors
        3. 9.2.2.3 Step-down Converter Inductors
        4. 9.2.2.4 LDO Input Capacitors
        5. 9.2.2.5 LDO Output Capacitors
        6. 9.2.2.6 VCC7
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

PFP Package, 0.5-mm Pitch
80-Pin HTQFP With Thermal Pad
Top View
TPS659119-Q1 po_swcs106.gif

Pin Functions

PIN TYPE I/O DESCRIPTION SUPPLIES PU / PD
NAME NO.
LDO8 1 Power O LDO regulator output VCC3, REFGND PD 5 µA
PWRHOLD 2 Digital I Switch-on, switch off control signal and GPI VRTC, DGND Programmable PD
(default active)
PWRDN 3 Analog I Reset input, for example, thermal reset VRTC, DGND PD
LDO6 4 Power O LDO regulator output VCC3, REFGND PD 5 µA
5
VCC3 6 Power I LDO6 and LDO7 power Input VCC3, AGND2 No
LDO7 7 Power O LDO regulator output VCC3, REFGND PD 5 µA
GPIO0 8 Digital I/O GPIO, push pull and OD as output VCC7, DGND OD: external PU
LDO2 9 Power O LDO regulator output VCC6, REFGND No
10
VCC6 11 Power I LDO1, LDO2 power Input VCC6, AGND2 No
12
LDO1 13 Power O LDO regulator output VCC6, REFGND No
14
SDA_SDI 15 Digital I/O I2C bidirectional-data signal and serial-peripheral-interface data input (multiplexed) VDDIO, DGND External PU
SCL_SCK 16 Digital I/O I2C bidirectional-clock signal and serial-peripheral-interface clock input (multiplexed) VDDIO, DGND External PU
EN2 17 Digital I/O Enable for supplies and voltage scaling dedicated to I2C data VDDIO, DGND External PU
EN1 18 Digital I/O Enable for supplies and voltage scaling dedicated to I2C clock VDDIO, DGND External PU
VDDIO 19 Power I Digital I/O supply VDDIO, DGND No
AGND2 20 Power I/O Analog ground AGND2 No
VCCIO 21 Power I VIO DC-DC power Input VCCIO, GNDIO No
22
SWIO 23 Power O VIO DC-DC switched output VCCIO, GNDIO No
24
GNDIO 25 Power I/O VIO DC-DC power ground VCCIO, GNDIO No
26
GPIO4 27 Digital I/O GPIO VRTC, DGND OD: External PU
OD
VFBIO 28 Analog I VIO feedback voltage VCC7, DGND PD 5 µA
HDRST 29 Digital I Cold reset VRTC, DGND PD
REFGND 30 Analog I/O Reference ground REFGND No
VREF 31 Analog O Bandgap voltage VCC7, REFGND No
GPIO5 32 Digital I/O GPIO VRTC, DGND OD: external PU
OD
BOOT1 33 Digital I Power-up sequence selection VRTC, DGND No
GPIO1 34 Digital I/O GPIO and LED1 output VRTC, DGND OD: External PU
OD
OSC16MIN 35 Analog I 16.384-MHz crystal oscillator input VCC7, DGND External PD if not in use
OSC16MOUT 36 Analog O 16.384-MHz crystal oscillator output VCC7, DGND No
OSCEXT32K 37 Digital I External 32-kHz clock input VRTC, DGND External PD if not in use
LDO3 38 Power O LDO regulator output VCC5, REFGND PD 5 µA
VCCS 39 Analog I/O VCC7 voltage sense input VCC7, DGND No
VCC5 40 Power I LDO3 and LDO4 power Input VCC5, AGND No
LDO4 41 Power O LDO regulator output VCC5, REFGND PD 5 µA
TESTV 42 Analog O Analog test output (DFT) VCC7, AGND No
GPIO3 43 Digital I/O GPIO and LED2 output VRTC, DGND OD: External PU
OD
NRESPWRON2 44 Digital O Second NRESPWRON output VRTC, DGND PD active during device OFF state.External pullup when ACTIVE
OD
VBACKUP 45 Power I Tie this pin to AGND VBACKUP, AGND No
AGND 46 Power I/O Analog ground AGND No
VCC7 47 Power I VRTC power input and analog references supply VCC7, REFGND No
VRTC 48 Power O LDO regulator output VCC7, REFGND PD 5 µA
AGNDEX 49 Power I/O EXTCTRL resistive divider ground AGNDEX No
VSENSE 50 Analog I EXTCTRL resistive divider output VOUT, AGNDEX No
EN 51 Digital O EXTCTRL enable signal for external converter VCC7, DGND No
VOUT 52 Analog I EXTCTRL resistive divider input VOUT, AGNDEX No
DGND 53 Power I/O Digital ground DGND No
VFB1 54 Analog I VDD1 feedback voltage VCC7, DGND PD 5 µA
PWRON 55 Digital I External switch-on control (ON button) VCC7, DGND Programmable PU
(default active)
GND1 56 Power I/O VDD1 DC-DC power ground VCC1, GND1 No
57
SW1 58 Power O VDD1 DC-DC switched output VCC1, GND1 No
59
VCC1 60 Power I VDD1 DC-DC power Input VCC1, GND1 No
61
SLEEP 62 Digital I ACTIVE-SLEEP state transition control signal VDDIO, DGND Programmable PD
(default active)
GPIO8 63 Digital I/O, OD GPIO VRTC, DGND OD: External PU
CLK32KOUT 64 Digital O 32-kHz clock output VDDIO, DGND PD, disabled in ACTIVE or SLEEP state
GPIO6 65 Digital I/O, OD GPIO VRTC, DGND OD: External PU
NRESPWRON 66 Digital O Power off reset VDDIO, DGND PD active during device OFF state
VCC2 67 Power I VDD2 DC-DC power input VCC2, GND2 No
68
SW2 69 Power O VDD2 DC-DC switched output VCC2, GND2 No
70
GND2 71 Power I/O VDD2 DC-DC power ground VCC2, GND2 No
72
GPIO7 73 Digital I/O, OD GPIO VRTC, DGND OD: External PU
VFB2 74 Analog I VDD2 DC-DC feedback voltage VCC7, DGND PD 5 µA
INT1 75 Digital O Interrupt flag VDDIO, DGND No
GPIO2 76 Digital I/O, OD GPIO and DC-DC clock synchronization VRTC, DGND OD: External PU
LDO5 77 Power O LDO regulator output VCC4, REFGND PD 5 µA
78
VCC4 79 Power I LDO5 power input VCC4, AGND2 No
VCC8 80 Power I LDO8 power input VCC8, AGND2 No