SLVSDM1A August   2017  – February 2019 TPS65919-Q1

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
      1.      Pin Attributes
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics — LDO Regulators
    6. 4.6  Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
    7. 4.7  Electrical Characteristics — SMPS1, SMPS2, SMPS3, and SMPS4 Stand-Alone Regulators
    8. 4.8  Electrical Characteristics — Reference Generator (Bandgap)
    9. 4.9  Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    10. 4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
    11. 4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
    12. 4.12 Electrical Characteristics — System Control Thresholds
    13. 4.13 Electrical Characteristics — Current Consumption
    14. 4.14 Electrical Characteristics — Digital Input Signal Parameters
    15. 4.15 Electrical Characteristics — Digital Output Signal Parameters
    16. 4.16 I/O Pullup and Pulldown Characteristics
    17. 4.17 Electrical Characteristics — I2C Interface
    18. 4.18 Timing Requirements — I2C Interface
    19. 4.19 Timing Requirements — SPI
    20. 4.20 Switching Characteristics — LDO Regulators
    21. 4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
    22. 4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, and SMPS4 Stand-Alone Regulators
    23. 4.23 Switching Characteristics — Reference Generator (Bandgap)
    24. 4.24 Switching Characteristics — PLL for SMPS Clock Generation
    25. 4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    26. 4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
    27. 4.27 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Device State Machine
      1. 5.3.1  Embedded Power Controller
      2. 5.3.2  State Transition Requests
        1. 5.3.2.1 ON Requests
        2. 5.3.2.2 OFF Requests
        3. 5.3.2.3 SLEEP and WAKE Requests
      3. 5.3.3  Power Sequences
      4. 5.3.4  Device Power Up Timing
      5. 5.3.5  Power-On Acknowledge
        1. 5.3.5.1 POWERHOLD Mode
        2. 5.3.5.2 AUTODEVON Mode
      6. 5.3.6  BOOT Configuration
        1. 5.3.6.1 Boot Pin Usage and Connection
      7. 5.3.7  Reset Levels
      8. 5.3.8  INT
      9. 5.3.9  Warm Reset
      10. 5.3.10 RESET_IN
    4. 5.4  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
      1. 5.4.1 Step-Down Regulators
        1. 5.4.1.1 Output Voltage and Mode Selection
        2. 5.4.1.2 Clock Generation for SMPS
        3. 5.4.1.3 Current Monitoring and Short Circuit Detection
        4. 5.4.1.4 POWERGOOD
        5. 5.4.1.5 DVS-Capable Regulators
          1. 5.4.1.5.1 Non DVS-Capable Regulators
        6. 5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
        7. 5.4.1.7 Step-Down Converters SMPS3, and SMPS4
      2. 5.4.2 Low Dropout Regulators (LDOs)
        1. 5.4.2.1 LDOVANA
        2. 5.4.2.2 LDOVRTC
        3. 5.4.2.3 LDO1 and LDO2
        4. 5.4.2.4 Low-Noise LDO (LDO5)
        5. 5.4.2.5 Other LDOs
    5. 5.5  SMPS and LDO Input Supply Connections
    6. 5.6  First Supply Detection
    7. 5.7  Long-Press Key Detection
    8. 5.8  12-Bit Sigma-Delta General-Purpose ADC (GPADC)
      1. 5.8.1 Asynchronous Conversion Request (SW)
      2. 5.8.2 Periodic Conversion (AUTO)
      3. 5.8.3 Calibration
    9. 5.9  General-Purpose I/Os (GPIO Pins)
    10. 5.10 Thermal Monitoring
      1. 5.10.1 Hot-Die Function (HD)
      2. 5.10.2 Thermal Shutdown
    11. 5.11 Interrupts
    12. 5.12 Control Interfaces
      1. 5.12.1 I2C Interfaces
        1. 5.12.1.1 I2C Implementation
        2. 5.12.1.2 F/S Mode Protocol
        3. 5.12.1.3 HS Mode Protocol
      2. 5.12.2 Serial Peripheral Interface (SPI)
        1. 5.12.2.1 SPI Modes
        2. 5.12.2.2 SPI Protocol
    13. 5.13 OTP Configuration Memory
    14. 5.14 Watchdog Timer (WDT)
    15. 5.15 System Voltage Monitoring
    16. 5.16 Register Map
      1. 5.16.1 Functional Register Mapping
    17. 5.17 Device Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 SMPS Input Capacitors
        2. 6.2.2.2 SMPS Output Capacitors
        3. 6.2.2.3 SMPS Inductors
        4. 6.2.2.4 LDO Input Capacitors
        5. 6.2.2.5 LDO Output Capacitors
        6. 6.2.2.6 VCCA
          1. 6.2.2.6.1 Meeting the Power-Down Sequence
          2. 6.2.2.6.2 Maintaining Sufficient Input Voltage
        7. 6.2.2.7 VIO_IN
        8. 6.2.2.8 GPADC
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Coupling and Bulk Capacitors
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Third-Party Products Disclaimer
      2. 7.1.2 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.11 Interrupts

Table 5-12 lists the TPS65919-Q1 interrupts.

These interrupts are split into four register groups (INT1, INT2, INT3, and INT4) and each group has three associated control registers which are defined as follows:

    INTx_STATUSReflects which interrupt source has triggered an interrupt event
    INTx_MASKUsed to mask any source of interrupt, to avoid generating an interrupt on a specified source
    INTx_LINE_STATEReflects the real-time state of each line associated to each source of interrupt

The INT4 register group has two additional registers, INT4_EDGE_DETECT1 and
INT4_EDGE_DETECT2, to independently configure rising and falling edge detection (respectively).

All interrupts are logically combined on a single output line, INT (default is active low). The INT line is used as an external interrupt line to warn the host processor of any interrupt event that has occurred within the device. The host processor must read the interrupt status registers (INTx_STATUS) through the control interface (I2C) to identify the interrupt source. Any interrupt source can be masked by programming the corresponding mask register, INTx_MASK. When an interrupt is masked, the associated event-detection mechanism is disabled. Therefore the corresponding STATUS bit is not updated and the INT line is not triggered if the masked event occurs. If an event occurs while the corresponding interrupt is masked, that event is not recorded. If an interrupt is masked after it has been triggered (the event has occurred and has not been cleared), the STATUS bit would reflect the event until the bit is cleared. While the event is masked, the STATUS bit will not be over-written when a new event occurs.

Because some interrupts are sources of ON requests (see Table 5-12), source masking can mask a specific device switch-on event. Because an active interrupt line, INT, is treated as an ON request, any interrupt that is not masked must be cleared to allow the execution of a sleep sequence of the device, when requested.

The polarity of the INT line and clearing method of interrupts can be configured using the INT_CTRL register.

An INT line can be triggered in either SLEEP or ACTIVE state, depending on the setting of the OSC_THERM_CTRL.INT_MASK_IN_SLEEP bit.

When a new interrupt occurs while the INT line is still active (not all interrupts are cleared), then the following occurs:

  • If the new interrupt source is the same as the one that has already triggered the INT line, the interrupt can be discarded or stored as a pending interrupt depending on the setting of the
    INT_CTRL.INT_PENDING bit.
    • When the INT_CTRL.INT_PENDING bit is active, then any new interrupt event occurring on the same source (while the INT line is still active) is stored as a pending interrupt. Because only one level of pending interrupts can be stored for a given source, when more than two events occur on the same source, only the last event is stored. While an interrupt is pending, two accesses are required (either read or write) to clear the STATUS bit: one access for the actual interrupt and the other for the pending interrupt. Two consecutive read-write (R/W) operations to the same register clear only one interrupt. Another register must be accessed between the two R/W clear operations.

      • For example of a clear-on-read operation, when the INT signal is active, read all four INTx_STATUS registers in sequence to collect the status of all potential interrupt sources. The read access clears the full register for the active or actual interrupt. If the INT line is still active, repeat the read sequence to check and clear pending interrupts.

    • When the INT_CTRL.INT_PENDING bit is inactive (default), then any new interrupt event occurring on the same source (while the INT line is still active) is discarded. Two consecutive R/W operations to the same register only clear one interrupt. Another register must be accessed between the two R/W-to-clear operations.
  • If the new interrupt source is different from the one that already triggered the INT line, then the interrupt is stored immediately in the corresponding STATUS bit.

To clear the interrupt line, all status registers must be cleared. The clearing of all status registers occurs by using a clear-on-read or a clear-on-write method. The clearing method is selectable though the INT_CTRL.INT_CLEAR bit. When this bit is set, the clearing method applies to all bits for all interrupts.

The two different clear operations are defined as follows:

    Clear-on-readRead operation on a single status register clears all bits for only this specific register (8 bits). Therefore, a read operation of all the four status registers is required to clear all the interrupts requests. When the four read operations are complete, if the INT line is still active then another interrupt event has occurred during the read process. Therefore, the read sequence must be repeated.
    Clear-on-writeThis method is bit-based; setting a specific bit to 1 clears only the written bit. Therefore, to clear a complete status register, write 0xFF. Writing 0xFF to all four status registers is required to clear all the interrupt requests. When the four write operations are complete, if the INT line is still active then another interrupt event has occurred during the write process. Therefore the write sequence must be repeated.

Table 5-12 Interrupt Sources

INTERRUPT ASSOCIATED EVENT EDGES DETECTION ON REQUEST REG. GROUP REG. BIT DESCRIPTION
VSYS_MON Internal event Rising and falling Never INT1 6 System voltage monitoring interrupt
Triggered when the system voltage crosses the configured threshold in the VSYS_MON register.
HOTDIE Internal event Rising and Falling Never 5 Hot-die temperature interrupt
The embedded thermal monitoring module has detected a die temperature above the hot-die detection threshold. An interrupt is generated in ACTIVE and SLEEP states, not in OFF state.
PWRDOWN PWRDOWN (pin) Rising and falling Never 4 Power-down interrupt
Triggered when event is detected on the PWRDOWN pin.
LONG_PRESS_KEY PWRON (pin) Falling Never 2 Power-on long key-press interrupt
Triggered when PWRON is low during more than the long-press delay, LONG_PRESS_KEY.LPK_TIME.
PWRON PWRON (pin) Falling Always (INT mask, don't care) 1 Power-on interrupt
Triggered when the PWRON button is pressed (low) while the device is on. An interrupt is generated in ACTIVE and SLEEP states, not in OFF state.
SHORT Internal event Rising Yes (if INT not masked) INT2 6 Short interrupt
Triggered when at least one of the power resources (SMPS or LDO) outputs is shorted.
FSD Internal event Rising Yes (if INT not masked) 5 First supply detection interrupt
Triggered when a first supply detection is detected. This functions is selected by PMU_SECONDARY_INT.FSD_MASK.
RESET_IN RESET_IN (pin) Rising Never 4 RESET_IN interrupt
Triggered when event is detected on the RESET_IN pin.
WDT Internal event Rising Never 2 Watchdog time-out interrupt
Triggered when watchdog time-out expires.
OTP_ERROR Internal event Rising Never 1 OTP bit error detection interrupt
Triggered when an OTP bit error is detected.
VBUS VBUS (pin) Rising and falling Yes (if INT not masked) INT3 7 VBUS wake-up comparator interrupt
Active in OFF state. Triggered when VBUS present.
GPADC_EOC_SW Internal event N/A Yes (if INT not masked) 2 GPADC software end-of-conversion interrupt
Triggered when the conversion result is available.
GPADC_AUTO_1 Internal event N/A Yes (if INT not masked) 1 GPADC automatic periodic conversion 1
Triggered when the result of a conversion is either above or below (depending on configuration) reference threshold GPADC_AUTO_CONV1_LSB and GPADC_AUTO_CONV1_MSB.
GPADC_AUTO_0 Internal event N/A Yes (if INT not masked) 0 GPADC automatic periodic conversion 0
Triggered when the result of a conversion is either above or below (depending on configuration) reference threshold GPADC_AUTO_CONV0_LSB and GPADC_AUTO_CONV0_MSB.
GPIO_6 GPIO_6 (pin) Rising, falling, or both Yes (if INT not masked) INT4 6 GPIO_6 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_5 GPIO_5 (pin) Rising, falling, or both Yes (if INT not masked) 5 GPIO_5 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_4 GPIO_4 (pin) Rising, falling, or both Yes (if INT not masked) 4 GPIO_4 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_3 GPIO_3 (pin) Rising, falling, or both Yes (if INT not masked) 3 GPIO_3 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_2 GPIO_2 (pin) Rising, falling, or both Yes (if INT not masked) 2 GPIO_2 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_1 GPIO_1 (pin) Rising, falling, or both Yes (if INT not masked) 1 GPIO_1 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges
GPIO_0 GPIO_0 (pin) Rising, falling, or both Yes (if INT not masked) 0 GPIO_0 rising-edge detection interrupt, falling-edge detection interrupt, or detection interrupt for both edges