SLVSAI3A September   2010  – May 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Transient Response
      3. 7.3.3 Reverse Current
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Pin and Shutdown
      2. 7.4.2 Dropout Voltage
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Circuit for Fixed-Voltage Versions
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input And Output Capacitor Requirements
          2. 8.2.1.2.2 Output Noise
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application Circuit for Adjustable-Voltage Version
        1. 8.2.2.1 Design Requirements
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
  11. 11Device And Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, And Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Solder pad footprint recommendations for the TPS736xx-Q1 are presented in Solder Pad Recommendations for Surface-Mount Devices, SBFA015.

10.2 Layout Example

TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 layout_fixed_slvsai3.gif Figure 35. Fixed-Output Voltage Option Layout
TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 layout_adjustable_slvsai3.gif Figure 36. Adjustable-Output Voltage Option Layout

10.3 Thermal Considerations

The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improve the heat sink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), shown in Equation 6:

Equation 6. TPS73601-Q1 TPS73625-Q1 TPS73633-Q1 Q_pd_vinvout-bvs038.gif

Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage.

10.4 Power Dissipation

To improve AC performance such as PSRR, output noise, and transient response, TI recommends that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the GND pin of the device.