SBVS074L January   2007  – March 2017

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics IOUT = 50 mA
    7. 6.7 Typical Characteristics IOUT = 1 A
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable/Shutdown
      2. 7.3.2 Power Good
      3. 7.3.3 Internal Current Limit
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
    2. 8.2 Typical Applications
      1. 8.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • VOUT Range: 0.8 V to 3.6 V
  • Ultralow VIN Range: 0.8 V to 5.5 V
  • VBIAS Range 2.7 V to 5.5 V
  • Low Dropout: 60 mV Typical at 1.5 A, VBIAS = 5 V
  • Power Good (PG) Output Allows Supply Monitoring or Provides a Sequencing Signal for Other Supplies
  • 2% Accuracy Over Line, Load, and Temperature
  • Programmable Soft-Start Provides Linear Voltage Startup
  • VBIAS Permits Low VIN Operation With Good Transient Response
  • Stable With Any Output Capacitor ≥ 2.2 μF
  • Available in a Small, 3-mm × 3-mm × 1-mm VSON-10 and 5 × 5 QFN-20 Packages

Applications

  • FPGA Applications
  • DSP Core and I/O Voltages
  • Post-Regulation Applications
  • Applications With Special Start-up Time or Sequencing Requirements
  • Hot-Swap and Inrush Controls

Description

The TPS748 low-dropout (LDO) linear regulator provides an easy-to-use robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well-suited for powering many different types of processors and ASICs. The enable input and power good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2 μF, and is fully specified for TJ = –40°C to 125°C. The TPS748 is offered in a small, 3-mm × 3-mm, VSON-10 package, yielding a highly compact, total solution size. The device is also available in a 5 × 5 QFN-20 package for compatibility with the TPS744.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS748 VSON (10) 3.00 mm x 3.00 mm
VQFN (20) 5.00 mm x 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

SPACE

SPACE

SPACE

Typical Application Circuit (Adjustable)

TPS748 front_fig_bvs074.gif

Turnon Response

TPS748 tc_turn_on_bvs074.gif