SBVS171F December   2011  – October 2015 TPS7A16

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Regulated Output (VOUT)
      3. 7.3.3 Power-Good
      4. 7.3.4 PG Delay Timer (DELAY)
      5. 7.3.5 Internal Current Limit
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS7A1601 Circuit as an Adjustable Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Adjustable Voltage Operation
            1. 8.2.1.2.1.1 Resistor Selection
            2. 8.2.1.2.1.2 Capacitor Recommendations
            3. 8.2.1.2.1.3 Input and Output Capacitor Requirements
            4. 8.2.1.2.1.4 Feed-Forward Capacitor
            5. 8.2.1.2.1.5 Transient Response
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Automotive Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Device Recommendations
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Multicell Battery Packs
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
      4. 8.2.4 Battery-Operated Power Tools
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Additional Layout Considerations
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
    4. 10.4 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range –40°C ≤ TJ ≤ 125°C (unless otherwise noted).(1)
MIN MAX UNIT
Voltage IN pin to GND pin –0.3 62 V
OUT pin to GND pin –0.3 20
OUT pin to IN pin –62 0.3
FB pin to GND pin –0.3 3
FB pin to IN pin –62 0.3
EN pin to IN pin –62 0.3
EN pin to GND pin –0.3 62
PG pin to GND pin –0.3 5.5
DELAY pin to GND pin –0.3 5.5
Current Peak output Internally limited
Temperature Operating virtual junction, TJ –40 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Unregulated input 3 60 V
VOUT Regulated output 1.169 18.5 V
EN 0 40 V
DELAY 0 5 V
PG 0 5 V
TJ Operating junction temperature range –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS7A1601 UNIT
DGN (HVSSOP) DRB (VSON)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 66.2 44.5 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 45.9 49.5 °C/W
RθJB Junction-to-board thermal resistance 34.6 11.3 °C/W
ψJT Junction-to-top characterization parameter 1.9 0.7 °C/W
ψJB Junction-to-board characterization parameter 34.3 11.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 14.9 4.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At TJ = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 3 60 V
VREF Internal reference TJ = 25°C, VFB = VREF, VIN = 3 V, IOUT = 10 μA 1.169 1.193 1.217 V
VUVLO Undervoltage lockout threshold 2.7 V
VOUT Output voltage range VIN ≥ VOUT(NOM) + 0.5 V VREF 18.5 V
Nominal accuracy TJ = 25°C, VIN = 3 V, IOUT = 10 μA –2% 2% VOUT
Overall accuracy VOUT(NOM) + 0.5 V ≤ VIN ≤ 60 V(1)
10 µA ≤ IOUT ≤ 100 mA		 –2% 2% VOUT
ΔVO(ΔVI) Line regulation 3 V ≤ VIN ≤ 60 V ±1% VOUT
ΔVO(ΔIO) Load regulation 10 µA ≤ IOUT ≤ 100 mA ±1% VOUT
VDO Dropout voltage VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 20 mA 60 mV
VIN = 4.5 V, VOUT(NOM) = 5 V, IOUT = 100 mA 265 500 mV
ILIM Current limit VOUT = 90% VOUT(NOM), VIN = 3 V 101 225 400 mA
IGND Ground current 3 V ≤ VIN ≤ 60 V, IOUT = 10 µA 5 15 μA
IOUT = 100 mA 5 μA
ISHDN Shutdown supply current VEN = 0.4 V 0.59 5 μA
I FB Feedback current(2) –0.1 –0.01 0.1 µA
IEN Enable current 3 V ≤ VIN ≤ 12 V, VIN = VEN –1 –0.01 1 μA
VEN_HI Enable high-level voltage 1.2 V
VEN_LO Enable low- level voltage 0.3 V
VIT PG trip threshold OUT pin floating, VFB increasing, VIN ≥ VIN_MIN 85% 95% VOUT
OUT pin floating, VFB decreasing, VIN ≥ VIN_MIN 83% 93% VOUT
VHYS PG trip hysteresis 2.3% 4% VOUT
VPG, LO PG output low voltage OUT pin floating, VFB = 80% VREF, IPG= 1mA 0.4 V
IPG, LKG PG leakage current VPG= VOUT(NOM) –1 1 μA
IDELAY DELAY pin current 1 2 μA
PSRR Power-supply rejection ratio VIN = 3 V, VOUT(NOM) = VREF, COUT = 10 μF,
f = 100 Hz		 50 dB
TSD Thermal shutdown temperature Shutdown, temperature increasing 170 °C
Reset, temperature decreasing 150 °C
TJ Operating junction temperature range –40 125 °C
(1) Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT =
(24 V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as the power dissipated is within the thermal limits of the package plus any external heatsinking.
(2) IFB > 0 flows out of the device.

6.6 Typical Characteristics

At TJ = –40°C to 125°C, VIN = VOUT(NOM) + 0.5 V or VIN = 3 V (whichever is greater), VEN = VIN, IOUT = 10 µA, CIN = 1 μF, COUT = 2.2 μF, and FB tied to OUT, unless otherwise noted.
TPS7A16 tc_iq-vin_bvs171.png
Figure 1. Quiescent Current vs Input Voltage
TPS7A16 tc_ignd-io_bvs171.png
Figure 3. Ground Current vs Output Current
TPS7A16 tc_vfb-vin_bvs171.png
Figure 5. Feedback Voltage vs Input Voltage
TPS7A16 tc_vo-io_bvs171.png
Figure 7. Load Regulation
TPS7A16 tc_vopg-temp_bvs171.png
Figure 9. Power-Good Threshold Voltage vs Temperature
TPS7A16 tc_psrr-freq_bvs171.png
Figure 11. Power-Supply Rejection Ratio
TPS7A16 tc_pg-delay_bvs171.gif
Figure 13. Power-Good Delay
TPS7A16 tc_ishdn-vin_bvs171.png
Figure 2. Shutdown Current vs Input Voltage
TPS7A16 tc_vdo-io_bvs171.png
Figure 4. Dropout Voltage vs Output Current
TPS7A16 tc_vo-vin_bvs171.png
Figure 6. Line Regulation
TPS7A16 tc_ilim-vin_bvs171.png
Figure 8. Current Limit vs Input Voltage
TPS7A16 tc_ven-temp_bvs171.png
Figure 10. Enable Threshold Voltage vs Temperature
TPS7A16 tc_vonoise-freq_bvs171.png
Figure 12. Output Spectral Noise Density