SBVS171F December   2011  – October 2015 TPS7A16


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Regulated Output (VOUT)
      3. 7.3.3 Power-Good
      4. 7.3.4 PG Delay Timer (DELAY)
      5. 7.3.5 Internal Current Limit
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS7A1601 Circuit as an Adjustable Regulator
        1. Design Requirements
        2. Detailed Design Procedure
          1. Adjustable Voltage Operation
            1. Resistor Selection
            2. Capacitor Recommendations
            3. Input and Output Capacitor Requirements
            4. Feed-Forward Capacitor
            5. Transient Response
        3. Application Curves
      2. 8.2.2 Automotive Applications
        1. Design Requirements
        2. Detailed Design Procedure
          1. Device Recommendations
        3. Application Curves
      3. 8.2.3 Multicell Battery Packs
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 8.2.4 Battery-Operated Power Tools
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Additional Layout Considerations
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
    4. 10.4 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

To improve AC performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device.

Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure stability. Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability.

If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout pattern used for TPS7A16 evaluation board, available at

10.1.1 Additional Layout Considerations

The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple undesirable signals from near-by components (specially from logic and digital ICs, such as microcontrollers and microprocessors); these capacitively-coupled signals may produce undesirable output voltage transients. In these cases, TI recommends using a fixed-voltage version of the TPS7A16, or isolate the FB node by flooding the local PCB area with ground-plane copper to minimize any undesirable signal coupling.

10.2 Layout Example

Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with a X5R or X7R dielectric.

It may be possible to obtain acceptable performance with alternative PCB layouts; however, the layout and the schematic have been shown to produce good results and are meant as a guideline.

Figure 21 shows the schematic for the suggested layout. Figure 22 and Figure 23 show the top and bottom printed-circuit-board (PCB) layers for the suggested layout.

TPS7A16 layout_ex_sbvs171.gif Figure 21. Schematic for Suggested Layout
TPS7A16 ai_pcb_top_bvs171.gif Figure 22. Suggested Layout: Top Layer
TPS7A16 ai_pcb_bot_bvs171.gif Figure 23. Suggested Layout: Bottom Layer

10.3 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element, as shown in Equation 2:

Equation 2. TPS7A16 q_pd_bvs125.gif

10.4 Thermal Considerations

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat spreading area. For reliable operation, junction temperature should be limited to a maximum of +125°C at the worst case ambient temperature for a given application. To estimate the margin of safety in a complete design (including the copper heat-spreading area), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +45°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS7A16 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A16 into thermal shutdown degrades device reliability.