SBVS256A May   2016  – September 2016 TPS7A19

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Pin (EN)
      2. 7.3.2 Regulated Output Pin (OUT)
      3. 7.3.3 Power-Good Pin (PG)
      4. 7.3.4 Delay Timer Pin (DELAY)
      5. 7.3.5 Adjustable Output Voltage (ADJ for TPS7A1901)
      6. 7.3.6 Undervoltage Shutdown
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 4 V
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation and Thermal Considerations
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range –40°C to 125°C(unless otherwise noted)(1)
MIN MAX UNIT
Voltage(3) Input IN, EN –0.3 45 V
Output OUT(2) –0.3 VIN + 0.3
DELAY(4) –0.3 45
FB, PG –0.3 22
Current Peak output Internally limited
Temperature Operating junction, TJ –40 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is VIN + 0.3 V or 22 V, whichever is lower.
(3) All voltage values are with respect to GND.
(4) The voltage at the DELAY pin must be lower than the VIN voltage.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Input supply voltage 4 40 V
VOUT Output voltage 1.5 18 V
VEN Enable voltage 0 40 V
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS7A19 UNIT
DRB (VSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 48 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.3 °C/W
RθJB Junction-to-board thermal resistance 22.4 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 22.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.6 °C/W
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at TJ = –40°C to +125°C, VIN = 14 V , VEN = VIN, IOUT = 200 μA, CIN = 22 μF, and COUT = 47 μF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT
VIN Input voltage VOUT ≤ 3.5 V , IOUT = 0 mA to 450 mA 4 40 V
VOUT ≥ 3.5 V , IOUT = 0 mA to 450 mA VOUT + 0.5 40 V
IQ Quiescent current VIN = 4 V to 40 V, VOUT = 1.5 V, VEN = 5 V, IOUT = 0.2 mA 15 25 µA
VIN = 18.5 V to 40 V, VOUT = 18 V, VEN = 5 V, IOUT = 0.2 mA 25 40
ISHDN Shutdown current VEN = 0 V, IOUT = 0 mA , VIN = 18 V, VOUT = 1.5 V 4 µA
VFB Feedback voltage Reference voltage for FB pin 1.208 1.233 1.258 V
VIN_UVLO Undervoltage lockout Ramp VIN down until output is turned off 2.6 V
UVLOHys Undervoltage detection hysteresis VIN rising 1 V
ENABLE INPUT (EN)
VEN_LO Logic input low level 0 0.4 V
VEN_HI Logic input high level 1.7 V
IEN EN pin current VEN = 40 V , VIN = 14 V 1 µA
REGULATED OUTPUT
VOUT Regulated output(1) VIN = VOUT + 1 V to 40 V and VIN ≥ 4 V,
IOUT = 100 µA to 450 mA 		–2% 2%
ΔVO(ΔVI) Line regulation VIN = VOUT + 1 V to 40 V and VIN ≥ 4 V, IOUT = 100 mA 10 mV
ΔVO(ΔIL) Load regulation IOUT = 1 mA to 450 mA, VIN = VOUT + 1 V and VIN ≥ 4 V 10 mV
VDO Dropout voltage VIN – VOUT, IOUT = 400 mA 240 450 mV
VIN – VOUT, IOUT = 200 mA 160 300
IOUT Output current VOUT in regulation 0 450 mA
ICL Output current-limit VOUT short to ground 140 360 mA
VOUT = VOUT nominal × 0.9 470 850
PSRR Power-supply ripple rejection(2) IOUT = 100 mA, COUT = 22 µF f = 100 Hz 60 dB
f = 100 kHz 40
PG
VOL PG output low voltage IOL = 0.5 mA 0.4 V
IOH PG leakage current PG pulled to VOUTwith 10-kΩ resistor 1 µA
VT(PG) Power good threshold VOUT power-up 89.6 91.6 93.6 % of VOUT
Vhys Hysteresis VOUT power-down 2 % of VOUT
PG DELAY
IDelay Delay capacitor charging current 5 9.5 14 µA
VT(PG_DLY) Delay pin comparator threshold voltage 1 V
TEMPERATURE
Tsd Junction shutdown temperature Temperature increasing 175 °C
Thys Hysteresis of thermal shutdown 24 °C
(1) Accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test. External resistor divider variation is not considered for accuracy measurement.
(2) Design information; not tested, specified by characterization.

6.6 Timing Requirements

MIN TYP MAX UNIT
TIMING FOR PG
tPG_DLY Power good delay C = delay-capacitor value capacitance = 100 nF(1) 10.5 ms
tPG-fixed Power good delay No capacitor on pin 325 µs
tPG(HL) PG falling propagation delay VOUT low to PG low 180 µs
(1) Information only; not tested in production. The equation is based on: (C × 1) / (9.5 × 10–6) = tPG_DLY, where C = delay capacitor value capacitance; range = 100 pF to 500 nF.

6.7 Typical Characteristics

at TJ = –40°C to +125°C, VIN = 14 V , VEN = VIN, IOUT = 200 μA, CIN = 22 μF, and COUT = 47 μF (unless otherwise noted)
TPS7A19 C001_SBVS256.gif
VOUT = 1.5 V, IOUT = 100 mA
Figure 1. Line Regulation
TPS7A19 C003_SBVS256.gif
VOUT = 1.5 V
Figure 3. Quiescent Current vs Input Voltage
TPS7A19 C005_SBVS256.gif
VOUT = 18 V
Figure 5. Quiescent Current vs Input Voltage
TPS7A19 C007_SBVS256.gif
VIN = 14 V, VOUT = 1.5 V
Figure 7. Load Regulation
TPS7A19 C013_SBVS256.png
Figure 9. Short to GND Current-Limit vs Temperature
TPS7A19 scope_load_transient_sbvs256.gif
Figure 11. Load Transient
10-µF Ceramic Output Capacitor
TPS7A19 C002_SBVS256.gif
VIN = 14 V, VOUT = 1.5 V
Figure 2. Ground Current vs Output Current
TPS7A19 C004_SBVS256.gif
VIN = 24 V, VOUT = 18 V
Figure 4. Ground Current vs Output Current
TPS7A19 C006_SBVS256.gif
Figure 6. Dropout Voltage vs Output Current
TPS7A19 C012_SBVS256.gif
VOUT = 5 V, COUT = 47 µF, IOUT = 10 mA
Figure 8. Power-Supply Rejection Ratio vs Frequency
TPS7A19 C014_SBVS256.png
Figure 10. Current-Limit vs Temperature