SBVS248A November 2015 – November 2015 TPS7A88
The TPS7A88 is a dual-channel, low-noise, high PSRR, low dropout (LDO) regulator capable of sourcing a 1-A load with only 200 mV of maximum dropout. The TPS7A88 can operate down to a 1.4-V input voltage and a 0.8-V output voltage. This combination of low-noise, high PSRR, and low dropout voltage makes the device an ideal LDO to power a multitude of loads from noise-sensitive communication components in high-speed communications applications to high-end microprocessors or field-programmable gate arrays (FPGAs).
As shown in the Functional Block Diagram section, each linear regulator features a low-noise, 0.8-V internal reference that can be filtered externally to obtain even lower output noise. The internal protection circuitry (such as the undervoltage lockout) prevents the device from turning on before the input is high enough to ensure accurate regulation. Foldback current limiting is also included that allows each output to source the rated output current when the output voltage is in regulation but reduce the allowable output current during short-circuit conditions. The internal power-good detection circuit allows users to sequence down-stream supplies and be alerted if the output voltage is below a regulation threshold.
The TPS7A88 consists of two completely independent linear regulators that can be used to replace two stand-alone LDOs, or to provide channel isolation for the same voltage input and outputs. Regardless of the implementation, the TPS7A88 provides excellent regulation to 1% accuracy, excellent dropout voltage, and high output current. If desired, the LDOs can be cascaded to achieve even higher PSRR by connecting the output of one channel to the input of the other channel.
Both channels of the TPS7A88 have an on-board charge pump that is always running to power the error amplifier to drive the gate of the n-channel pass-FET higher than the input voltage. The integrated charge pump allows the low dropout characteristics of the device to be maintained over the entire input voltage range of 1.4 V to 6.5 V.
The enable pins for the TPS7A88 are both active high. The output voltage for each channel is enabled when the corresponding enable pin voltage is greater than VIH(ENx) and disabled with the enable pin voltage is less than VIL(ENx). If control of the output voltage with the enable pin is not needed, then connect the enable pin to the corresponding input.
The TPS7A88 has an internal pulldown MOSFET that connects a 250-Ω resistor to ground when the device is disabled to actively discharge the output voltage.
Dropout voltage (VDO) is defined as the VINx – VOUTx voltage at the rated current (IRATED), where the main current pass-FET is fully on and in the ohmic region of operation. VDO indirectly specifies a minimum input voltage above the nominal programmed output voltage at which the output voltage is expected to remain in regulation. If the input falls below the nominal output regulation, then the output follows the input.
Dropout voltage is determined by the RDS(ON) of the main pass-FET. Therefore, if the LDO operates below the rated current, then the VDO for that current scales accordingly. The RDS(ON) for the TPS7A88 can be calculated using Equation 1:
Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent. The TPS7A88 features an output voltage accuracy of 1% that includes the errors introduced by the internal reference, load regulation, and line regulation variance across the full range of rated load and line operating conditions over temperature, as specified by the Electrical Characteristics table. Output voltage accuracy also accounts for all variations between manufacturing lots.
Each channel of the TPS7A88 includes a low-noise reference ensuring minimal output noise in normal operation. Adding a capacitor to the NR/SSx pins provides additional filtering to the internal reference, thus reducing the total output noise. The maximum value recommended for the NR/SSx capacitor is 1 µF. Further output noise reduction can be achieved by adding an external CFF between the SNS pin and the FBx pin.
Each input of the TPS7A88 has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input droops during turn on, the UVLO has approximately 285 mV of hysteresis.
The internal current limit circuit is used to protect the LDO against transient high-load current faults or shorting events. The LDO is not designed to operate in current limit under steady-state conditions. During an overcurrent event where the output voltage is pulled 10% below the regulated output voltage, the LDO sources a constant current as specified in the Electrical Characteristics table. When the output voltage falls, the amount of output current is reduced to better protect the device. During a hard short-circuit event, the current is reduced to approximately 1.25 A. See Figure 18 in the Typical Characteristics section for more information about the current limit foldback behavior. Note also that when a current-limit event occurs, the LDO begins to heat up because of the increase in power dissipation. The increase in heat can trigger the integrated thermal shutdown protection circuit.
Each LDO channel of the TPS7A88 contains a thermal shutdown protection circuit to turn off the output current when excessive heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (TJ) of the main pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the semiconductor die is fairly short, and thus the output turns on and off at a high rate when thermal shutdown is reached until power dissipation is reduced. Because there are two independent thermal shutdown circuits, one channel can be in thermal shutdown when the other channel is not.
The internal protection circuitry of the TPS7A88 is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A88 into thermal shutdown degrades device reliability.
For reliable operation, limit junction temperature to a maximum of 125°C. To estimate the thermal margin in a given layout, increase the ambient temperature until the thermal protection shutdown is triggered using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown must occur at least 40°C above the maximum expected ambient temperature condition for the application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after the ENx and UVLO thresholds are exceeded. The noise-reduction capacitor (CNR/SSx) serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on. Larger values for the noise-reduction capacitors decrease the noise but also result in a slower output turn-on ramp rate.
The TPS7A88 features an SS_CTRLx pin for each output. When this pin connected to INx the charging current for the NR/SSx pin is increased to 100 µA (typ). The higher current allows use of a much larger noise-reduction capacitor and still maintains a faster soft-start time. When the SS_CTRLx pin is connected to GND the charging current is reduced to 6.2 µA (typ), allowing a slower startup ramp rate. If a noise-reduction capacitor is not used on the NR/SSx pin, tying the SS_CTRLx pin to VIN can result in output voltage overshoot of approximately 10%. Any overshoot is minimized by connecting the SS_CTRLx pin to GND or using a capacitor on the NR/SSx pin. To achieve the lowest possible output noise, values for the noise-reduction capacitor can be as high as 10 µF. In this case, if a faster soft-start time is needed, connect the SS_CTRLx pin to VDD.
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. When the feedback pin voltage falls below the PG threshold voltage (VIT(PG)), the PGx pin open-drain output engages and pulls the PGx pin close to GND. When the feedback voltage exceeds the VIT(PG) threshold by an amount greater than VHYS(PG), the PGx pin becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can receive power good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. Using an external reset device such as the TPS3780 is also recommended in applications where high accuracy is needed or in applications where microprocessor resets are needed.
When employing the feed-forward capacitor (CFF), the turn-on time constant for the LDO is increased whereas the power-good output time constant stays the same, resulting in an invalid status of the LDO. To avoid this issue and to receive a valid PG output, ensure that the time constant of both the LDO and the power-good output are matching by adding a capacitor in parallel with the power-good pullup resistor. The state of PG is only valid when the device is operating above the minimum input voltage of the device and power good is asserted regardless of the output voltage state when the input voltage falls below the UVLO threshold minus the UVLO hysteresis. When the input voltage falls below approximately 0.8 V, there is not enough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output is falsely pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect.
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
|Normal(1)||VINx > VOUTx(nom) + VDO||VENx > VIH(ENx)||IOUTx < ICL||TJ < Tsd|
|Dropout(1)||VINx < VOUTx(nom) + VDO||VENx > VIH(ENx)||IOUTx < ICL||TJ < Tsd|
|Disabled(2)||UVLO||VENx < VIL(ENx)||—||TJ > Tsd|
The device regulates to the nominal output voltage when all of the following conditions are met.
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line or load transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VINx < VOUTx(NOM) + VDO, right after being in a normal regulation state, but not during startup), the pass-FET is driven as hard as possible when the control loop is out of balance. During the normal time required for the device to regain regulation, VINx ≥ VOUTx(NOM) + VDO, VOUTx overshoots if the input voltage slew rate is 0.1 V/µs or faster.
The outputs of the TPS7A88 can be shutdown by forcing the enable pins below 0.4 V. When disabled, the pass device is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal switch from the output to ground.