SBVS449 June   2026 TPS7B7802-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements - I2C Standard Mode
    7. 5.7 Timing Requirements - I2C Fast Mode
    8. 5.8 Timing Requirements - I2C Fast Mode Plus
    9. 5.9 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Under-Voltage Lockout (UVLO)
      2. 6.3.2  Enable
      3. 6.3.3  Output Voltage Setting
      4. 6.3.4  Soft Start
      5. 6.3.5  Voltage Monitoring
      6. 6.3.6  Current Monitoring
      7. 6.3.7  Reverse Current Protection
      8. 6.3.8  Current Limit
      9. 6.3.9  Junction Temperature Monitoring
      10. 6.3.10 Thermal Protection
      11. 6.3.11 Protection Features and Diagnostic Capabilities
      12. 6.3.12 NERR Pin
      13. 6.3.13 Blanking Time
      14. 6.3.14 Switch Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout
      3. 6.4.3 Operation with VIN < 4.5V
      4. 6.4.4 Disable
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
        1. 6.5.1.1 I2C Interface Speed
      2. 6.5.2 I2C Data Transfer Protocol
        1. 6.5.2.1 START and STOP
        2. 6.5.2.2 Logical 1's and 0's
        3. 6.5.2.3 Data Format
      3. 6.5.3 Address Frame
      4. 6.5.4 Write Cycle
      5. 6.5.5 Read Cycle
  8. 7 Register Map
    1. 7.1 Default Settings
    2. 7.2 Register Details
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Selection
        2. 8.2.2.2 Adjustable Device Feedback Resistor Selection
        3. 8.2.2.3 Feed-Forward Capacitor
        4. 8.2.2.4 Power Dissipation (PD)
        5. 8.2.2.5 Estimating Junction Temperature
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

6.5.4 Write Cycle

The TPS7B7802-Q1 device must be setup correctly by writing into the four configuration registers (CFGR0-3). For a detailed description on all the registers, please refer to the Register Map section. Table 6-3 lists the addresses and Read/Write (R/W) accessibility of all the registers in the TPS7B7802-Q1 device. The registers listed in Table 6-3 are 16 bits in size. Therefore 2 bytes of data can be read from or write into (if permissible) these registers.

Table 6-3 Register Map Summary
Index Register Name Address (Hex) Address (Binary) Read/Write
A3 A2 A1 A0
1 CFGR0 0 0 0 0 0 R/W
2 CFGR1 1 0 0 0 1 R/W
3 CFGR2 2 0 0 1 0 R/W
4 CFGR3 3 0 0 1 1 R/W
5 Data Register for device VIN 4 0 1 0 0 R
6 Data Register for Ch1VOUT 5 0 1 0 1 R
7 Data Register for Ch1IOUT-H 6 0 1 1 0 R
8 Data Register for Ch1IOUT-L 7 0 1 1 1 R
9 Data Register for Junction Temperature 8 1 0 0 0 R
10 Data Register for device VIN 9 1 0 0 1 R
11 Data Register for Ch2VOUT A 1 0 1 0 R
12 Data Register for Ch2IOUT-H B 1 0 1 1 R
13 Data Register for Ch2IOUT-L C 1 1 0 0 R
14 Latched Status Register D 1 1 0 1 R/W
15 Run Time Status Register E 1 1 1 0 R
16 Mask Register F 1 1 1 1 R/W

After addressing the desired target, to write into a particular register, we recommend that the 8-bit frame ‘Control Byte 0’ be utilized. Figure 6-6 shows the structure of this frame and Table 6-4 describes the function of each bit.

TPS7B7802-Q1 Structure of Control Byte 0 Figure 6-6 Structure of Control Byte 0
Table 6-4 Control Byte 0 Description
Bit Field Description
D7 Control Byte ID

0: Control Byte 0 (This Byte helps the user read/write data into registers).

1: Control Byte 1 (This Byte helps perform specific ADC functions).
D6 NA Must be ‘0’ for normal operation.
D5 A3

Register Address Bits
D4 A2
D3 A1
D2 A0
D1 NA Must be ‘0’ for normal operation.
D0 R/W

1: Data from register whose address correlates to the address bits can be read.

0: Data can be written into register whose address correlates to the address bits.

Table 6-5 lists an example configuration of the TPS7B7802-Q1 device. Figure 6-7 describes the process of populating the four configuration registers to get the configuration listed in Table 6-5. The Mask and the Latched Status register can be written into, in a similar way. The hex/binary codes corresponding to the various target values and the composition of configuration registers CFGR0-3 are provided in the Register Map section.

Table 6-5 Example setup
Parameter Channel 1 Channel 2
Target Value Binary Code Target Value Binary Code
Current Limit at Start-up 200mA 0111 300mA 1011
Load current warn threshold 310mA 1111 250mA 1100
Output Voltage 12V 0110 0100 10V 0101 0000
Open load threshold 10mA 1010 15mA 1111
Current Limit 350mA 1101 400mA 1111
Junction Temp warn threshold 130°C 110
ADC Enable Enable 1
Runtime/Latch Error Runtime 0
Blanking Time 8.5ms 100
Digital Enable Enable 1 Enable 1
External Feedback setting No 0 No 0
TPS7B7802-Q1 Write Cycle Example Figure 6-7 Write Cycle Example

The write accessible registers can be populated in any sequence and the STOP (or repeated START) sequence can be initiated at any time. To begin the re-write after a STOP, the target has to be addressed again the write cycle described above has to be repeated.

If data is attempted to be written into a read only accessible register, the TPS7B7802-Q1 device responds with a NACK. This is shown in Figure 6-8, where Control Byte 0 is sent with a write instruction to a read-only register (VIN register of LDO Ch-1) and TPS7B7802-Q1 the device responds with a NACK. The TPS7B7802-Q1 device continues to respond with a NACK, until the controller issues a STOP followed by a correct address frame.

TPS7B7802-Q1 Incorrect Write Cycle Figure 6-8 Incorrect Write Cycle