SBVS361B April   2020  – May 2025 TPS7B84-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable (EN)
      2. 6.3.2 Undervoltage Lockout
      3. 6.3.3 Thermal Shutdown
      4. 6.3.4 Current Limit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input and Output Capacitor Selection
      2. 7.1.2 Adjustable Device Feedback Resistor Selection
      3. 7.1.3 Feed-Forward Capacitor (CFF)
      4. 7.1.4 Dropout Voltage
      5. 7.1.5 Reverse Current
      6. 7.1.6 Power Dissipation (PD)
        1. 7.1.6.1 Thermal Performance Versus Copper Area
        2. 7.1.6.2 Power Dissipation vs Ambient Temperature
      7. 7.1.7 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Capacitor
        2. 7.2.2.2 Output Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Package Mounting
        2. 7.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCY|4
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.6.1 Thermal Performance Versus Copper Area

The most used thermal resistance parameter, RθJA, is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Thermal Information table in the Specifications section is determined by the JEDEC standard (see Figure 7-1), PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.

TPS7B84-Q1 JEDEC Standard 2s2p PCBFigure 7-1 JEDEC Standard 2s2p PCB

Figure 7-2 through Figure 7-4 depict the functions of RθJA and ψJB versus copper area and thickness. These plots are generated with a 101.6-mm x 101.6-mm x 1.6-mm PCB of two and four layers. For the four-layer board, the inner planes use a 1-oz copper thickness. Outer layers are simulated with both a 1-oz and 2-oz copper thickness. A 4 x 4 array of thermal vias of 300-µm drill diameter and 25-µm Cu plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area.

TPS7B84-Q1 RθJA vs Copper Area 2s2p DRB PackageFigure 7-2 RθJA vs Copper Area 2s2p DRB Package
TPS7B84-Q1 RθJA vs Copper Area 2s2p DCY PackageFigure 7-4 RθJA vs Copper Area 2s2p DCY Package
TPS7B84-Q1 ψJB vs Copper Area 2s2p DRB PackageFigure 7-3 ψJB vs Copper Area 2s2p DRB Package
TPS7B84-Q1 ψJB vs Copper Area 2s2p DCY PackageFigure 7-5 ψJB vs Copper Area 2s2p DCY Package