There are several considerations in determining the value of the output capacitor. The selection of the output capacitor is driven by:

1. The desired output voltage ripple, driven by the natural switching action of the power stage.
2. The allowable voltage deviation due to a large, abrupt change in load current (load step).

The output capacitance needs to be selected based on the more stringent of these two criteria (refer to Equation 33).When selecting the capacitors, care can be taken to select capacitors with a sufficient voltage rating, temperature rating, and consideration of any effective capacitance changes due to DC bias effects. Of importance is the note that the value of the output capacitor directly influences the modulator pole of the converter frequency response, as described in Section 9.2.2.9.

The first criteria to consider is the desired response to a load step. This generally occurs when the regulator is temporarily not able to supply sufficient output current during a large, fast increase in the current needs of the load. This can occur during a transition from no load to full load due to dynamic loads such as processors. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. Equation 34 shows the minimum output capacitance, from the electrical point of view, necessary to accomplish this. This is a first order approximation and does not take into condideration the ESR and ESL of the ourput capacitor. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. However, for space applications and large capacitance values, tantalum capacitors are typically used, which have a certain ESR value to take into consideration.

Where:

• ΔI_OUTx is the worst case change in load current (load step) in the application in Amps (A). In this case we are designing for a full-load step of 3A/phase.
• f_SW is the switching frequency of the converter in Hertz. In this case the selected switching frequency is 500kHz.
• ΔV_{OUTx_LOAD_STEP} is the allowed change in the output voltage due to the load step. In this case the target is to stay below a 3.5% change in the nominal output voltage.

The next criteria is to calculate the required capacitance to meet the output voltage ripple requirements using Equation 35. In this design, the maximum desired output voltage ripple is less than 0.8% of V_OUTx.

Where:

1. Δi_Lx is the ripple current in Amps (A). Refer to Table 9-3 for the values for each channel.
2. f_SW is the switching frequency of the converter in Hertz. In this case the selected switching frequency is 500kHz.
3. ΔV_{OUTx_RIPPLE} is the target output voltage ripple due to the switching nature of the converter. In this design the target is to be less than 0.8% of the nominal output voltage.

Finally, the ESR of the capacitor must be considered when meeting the output voltage ripple. The upper bound for the ESR can be calculated using Equation 36. The results for each channel are shown in Output Capacitor Design Calculations.

Additional capacitance deratings for aging, temperature, and DC bias should be factored in, which increases the minimum required output capacitance value. Capacitors generally have limits to the amount of ripple current capacitors can handle without failing or producing excess heat. The selected bank of output capacitors must handle the ripple current calculated using Equation 30. For the selected inductor and nominal output voltage the ripple current for each case is shown on Table 9-2.

For this specific design, taking into consideration all of the above requirements, a 470μF T55 Tantalum capacitors is selected for each channel. The selected capacitor have a max ESR of 7mΩ, and a maximum RMS current rating of 5.66A. Additionally, a 0.1μF ceramic capacitor is added in parallel for high frequency filtering. This results in a total capacitance of 470.1μF. Using Equation 37 we can calculate the expected ripple voltage at each channel, the results are shown in Table 9-5