SNVSCB8A march   2023  – april 2023 TPSF12C3

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Active EMI Filtering
        1. 8.3.1.1 Schematics
      2. 8.3.2 Capacitive Amplification
      3. 8.3.3 Integrated Line Rejection Filter
      4. 8.3.4 Compensation
      5. 8.3.5 Remote Enable
      6. 8.3.6 Supply Voltage UVLO Protection
      7. 8.3.7 Thermal Shutdown Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – AEF Circuit for Grid Infrastructure Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Sense Capacitors
          2. 9.2.1.2.2 Inject Capacitor
          3. 9.2.1.2.3 Compensation Network
          4. 9.2.1.2.4 Injection Network
          5. 9.2.1.2.5 Surge Protection
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Limits apply over the junction temperature (TJ) range of –40°C to 150°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VVDD = 12 V(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ VDD quiescent current SENSE1, SENSE2, SENSE3, and SENSE4 grounded, VEN = 5 V, 8 V ≤ VVDD ≤ 16 V  6.25 13.2 25.5 mA
SENSE1, SENSE2, SENSE3, and SENSE4 grounded, VEN = 5 V, VVDD = 12 V, TJ = 25°C 11 13.2 15.5
ISD VDD shutdown supply current VEN = 0 V 55 µA
SUPPLY VOLTAGE UVLO
VVDD-UV-R UVLO rising threshold VVDD rising 7.35 7.7 7.95 V
VVDD-UV-F UVLO falling threshold VVDD falling 6.4 6.7 7.0 V
VVDD-UV-HYS UVLO hysteresis 0.97 V
ENABLE
VEN-H EN voltage high 2.2 V
VEN-L EN voltage low 0.8 V
REN EN pin pull-up resistance to VDD VEN = 0 V 850 kΩ
IEN-LKG EN input leakage current VEN = 12 V 840 nA
INPUT FILTER NETWORK
ACM Gain from shorted power lines through single sense cap, CSEN, to COMP1 vs. REFGND CSEN = 2 µF(2), 60 Hz –44 dB
CSEN = 2 µF(2), 50 kHz –4
CSEN = 2 µF(2), 500 kHz(3)  –2
CSEN = 2 µF(2), 1 MHz(3)    –1
ADM Gain from differential signal applied to SENSE lines to COMP1 vs. REFGND SENSE1 shorted to SENSE2, SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 60 Hz		 –71 dB
SENSE1 shorted to SENSE2, SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 1 kHz		 –59
SENSE1 shorted to SENSE2, SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 500 kHz(3)  		 –42
SENSE1 shorted to SENSE2, SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 1 MHz(3)  		 –43
SENSE1 shorted to SENSE2, SENSE3 shorted to SENSE4,
CSEN1 = CSEN3 = 1 µF(2), 10 MHz(3)  		 –35
AMPLIFIER
ADC DC gain 52 58 69 dB
fBW Unity gain bandwidth(3) 113 MHz
fBW40 40 dB gain frequency 1 MHz
VOFST COMP1 offset voltage 2 V
VINJ-MAX Maximum output voltage for linear operation(3) COMP2 to INJ gain > 36 dB VVDD – 2 V
VINJ-MIN Minimum output voltage for linear operation(3) COMP2 to INJ gain > 36 dB 2.5 V
IINJ-MAX-OP INJ current at linearity limits(3) VINJ = VVDD – 2 V 80 mA
VINJ = VIGND + 2.5 V –80 mA
PSRR
PSRR10 10 pF in parallel with the series combination of 10 nF and 2 kΩ between COMP1 and COMP2, 10 kHz 0 dB
PSRR100 10 pF in parallel with the series combination of 10 nF and 2 kΩ between COMP1 and COMP2, 100 kHz 6
STARTUP
tW Startup delay(3)  Time from VDD = EN applied until output valid 43 ms
tSU EN high to valid output 42 ms
tSD EN low to stop output signal 0.32 µs
THERMAL SHUTDOWN
TJ-SHD Thermal shutdown threshold(3) Temperature rising 175 °C
TJ-HYS Thermal shutdown hysteresis(3) 20 °C
(1) MIN and MAX limits are 100% production tested at 25ºC unless otherwise specified. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Capacitance chosen for effective test only. Do not use this capacitance in applications.  
(3) Parameter specified by design, statistical analysis and production testing of correlated parameters.