SLVSFR3 April   2022 TPSI2140-Q1

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Safety-Related Certifications
    7. 6.7 Electrical Characteristics
    8. 6.8 Switching Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
      2. 8.3.2 Thermal Avalanche Protection (TAP)
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure Chassis Ground Reference
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DWQ|11
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Qualified for automotive applications
    • AEC-Q100 grade 1: –40 to 125°C ambient operating temperature
  • Integrated MOSFETs with 2-mA avalanche rating, up to 5 mA with TPSI2140T-Q1 version
    • 1400-V standoff voltage
    • RON = 130 Ω (TJ = 25°C)
    • TON, TOFF < 350 μs
  • Low primary side supply current
    • 7.5-mA ON state current
    • 6-μA OFF state current
  • Robust isolation barrier:
    • > 26 year projected lifetime at 1000-VRMS / 1414-VDC working voltage
    • Isolation rating, VISO, up to 3750 VRMS / 5300 VDC
    • Peak surge, VIOSM, up to 6000 V
    • ± 100-V/ns typical CMTI
  • SOIC (DWQ-11) package with wide pins for improved thermal capability
    • Creepage and clearance ≥ 8 mm (primary-secondary)
    • Creepage and clearance ≥ 6 mm (across switch terminals)
  • Safety-related certifications
    • (Planned) DIN VDE V 0884-11:2017-01
    • (Planned) UL 1577 component recognition program